User manual
CIP-ALL
CIP-ALL
- Page 35
•
Loopback:
With Loopback choice, you can configure manually the loopback on the E1 port,
local loopback
,
remote loopback
or
none
. With the
local analogue loopback
(ITU-T V54 B3 loop) the data from the E1 port are returned to the E1 port. With the
digital
loopback
(ITU-T V54-B2 loop), the data E1 from the TDM Bundle are returned to the TDM Bundle. The Loopback default is
none
.
5.3.15.
Ports LAN status
This table provides information about copper and optical Ethernet interfaces:
Status links are enabled or not, speed connection, transmit and receive bytes, transmit and receive rate for each port.
If an optical SFP module is inserted in a Gigabit Ethernet socket its main characteristics are displayed. For this example it is a 40 km 1000Base
LX module.
5.3.16.
Bundles Status
This page contains a list of Bundles and their activation.
At the top we find the information on each bundle with the IP address of remote IPC is displayed on top of this menu.
Then the reference clock status is presented.
The product operation may be described by these statuses :
•
Off: when the remote system is not connected.
•
Acquisition: during the clock acquisition from the remote CIP-ALL.
•
Tracking 1: the mechanism performs a precise phase-locked clock recovery
•
Tracking 2: the clock is synchronized, and the system keeps monitoring the remote clock.
•
Recovery from Underrun/Overrun: if the remote equipment is no longer available.
Some alarms may occur during these phases:
•
FRZ: the clock recovery mechanism is frozen.
•
DPLL: the clock went to overflow.
•
CDC: period of the clock recovery change in the network.
•
OVFL: overflow on the clock recovery filter.
•
JBO/U: le jitter buffer (JB) for the recovery clock is in under-run or over-run.
Transmit and receive packets statistics are displayed at the end of this menu..
The minimum and maximum jitter buffer delays indicate the minimum and maximum delay that took the transmitted frames.
Maximum Jitter Buffer should be monitored as it may be due to a clock issue, such as two units both set for internal clock.
