Curtiss-Wright SCRAMNet+ SC150e, Hardware Reference Manual

Page: 66 / 140

OPERATION
Copyright 2007 5-16 S SC150e HARDWARE REFERENCE
5.8.3 Interrupt Handling
The Interrupt FIFO is accessed via CSR4 and CSR5. CSR5 contains the most significant
seven bits of the 23-bit S SC150e interrupt address and CSR4 contains the
remaining 16 bits of the interrupt address. (The 23-bit address allows for future expansion
of memory). CSR5 also contains Interrupt FIFO Not Empty (bit 15).
NOTE
: The S SC150e Network is a longword (32-bit) oriented shared
memory. External Triggers and Interrupts will occur when any of the four bytes
associated with a longword are accessed. The Interrupt FIFO contains the longword
address. If each of the four bytes of an interrupt location are written into as byte
accesses, then four interrupts to the same longword address will be generated. Likewise,
if each word of an interrupt location is written into as 16-bit shortwords, then two
interrupts to the same longword address will be generated.
The CSR5 and CSR4 values make up the interrupt address. When an interrupt is received,
the ISR should read CSR5 first in order to check the Interrupt FIFO Not Empty bit. If this
bit is set (value is ‘1’), then read CSR4. If this bit is CLEAR (value is ‘0’) then the
Interrupt FIFO is empty. Therefore, the interrupt was due to an error, assuming that
Enable Interrupt On Error is set.
Every read from CSR5 and CSR4 will contain the S SC150e memory
address of the data received from the network interrupt. Every read of CSR5 and CSR4
will automatically increment the FIFO pointer to the next interrupt address for both
registers. CSR4 should be read only if Interrupt FIFO Not Empty CSR5[15] is set.
Continue to read CSR5 and CSR4 until the Interrupt FIFO Not Empty bit is zero. Writing
any value to CSR1 re-enables interrupts.
NOTE
: See Page 1-1 for an example of a standard ISR algorithm for handling interrupts
from the S SC150e cards.
.
WARNING
: If HIPRO is enabled, an interrupt may affect the sequence of addresses on
a read/write if S SC150e is manipulated in the ISR.
If an interrupt occurs before the interrupts have been armed, the interrupt will be placed
in the Interrupt FIFO and it will occur when the interrupts are armed (CSR 1).