Curtiss-Wright SCRAMNet+ SC150e, Hardware Reference Manual

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OPERATION
Copyright 2007 5-3 S SC150e HARDWARE REFERENCE
5.2.2 Memory Considerations
When using S SC150e shared-memory, consider the following:
PROGRAM AND DATA LIMITATIONS
Limitations on application program size and data variable size for a host computer system
also apply to applications using S SC150e memory because it becomes part
of the host system.
DATA CACHING
The ability for a computer to write a copy of data to a local fast memory for quicker
access later must be turned off during a S SC150e memory read. Since other
nodes may be changing the data, it is critical that the processor read the data directly from
S SC150e memory. This is processor-dependent and does not always apply.
MEMORY MAPPING
S SC150e memory is mapped by all operating systems in constant-length
blocks called memory pages.
NOTE
: To ensure that a compiler or operating system does not try to access unused
portions of S SC150e memory to store other program segments, declare the
S SC150e memory common blocks to be sized to an integer multiple of the
processor memory page size. If this is not done, most compilers will try to optimize
memory usage by filling out the S SC150e memory pages with other
data. This can cause random results when this local data is transmitted around the
network.
5.2.3 Control/Status Registers
The S SC150e cards are controlled through CSRs for node status, setting
interrupt vectors, setting interrupt locations, receiving interrupt addresses, mode control
and other functions. These registers may be accessed by linking to the I/O page and
reading from or writing to the registers as if they were memory. The method used to
access the registers depends on the particular computer and operating system being used.
These registers are set only during the S SC150e Network initialization.
Once the control portion of the CSR is set up for the desired mode operation, the node
functions as transparent shared memory and references to the CSRs are not required.
However, the status portions of the registers will need to be accessed for interrupt
servicing and for checking for error conditions. Appendix B: CSR DESCRIPTIONS
discusses the definition and use of each bit in the CSRs. Appendix C: CSR SUMMARY
contains a list of the CSRs and a brief identification of each bit.