Curtiss-Wright SCRAMNet+ SC150e, Hardware Reference Manual

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SCRAMNET OVERVIEW
Copyright 2007 2-3 S SC150e HARDWARE REFERENCE
2.2.2 Control/Status Registers (CSRs)
CSRs control the S SC150e card’s Input/Output (I/O) operations The location
of the CSRs in the computer’s address space is determined by the plug-and play BIOS in
the host system. You can find the CSRs address offsets in chapter 4: INSTALLATION.
Most modes of operation are set during initialization in registers embedded in the PCI
target controller, and remain unchanged during run time.
2.2.3 Virtual Paging
The S SC150e network may include a variety of S SC150e nodes
having varying amounts of shared memory. However, all S SC150e nodes
use the same 8 MB shared memory map. This feature permits different S
SC150e cards with 4 MB of shared memory or less to be paged into different sections of
the 8 MB memory map. A card with a 4 MB or smaller memory may be located on any
shared-memory address boundary that is an even multiple of itself (For example, 2 MB
can page to 0, 2, 4 or 6 MB address).
2.3 FIFO Buffers
The S SC150e card contains various FIFO buffers used for temporarily
storing information during normal send and receive operation of the node. Refer to Figure
2-1.
2.3.1 Transmit FIFO
The Transmit FIFO is a message holding area for native messages waiting to be
transmitted. Each host write to S SC150e memory may constitute a write to
the Transmit FIFO. (Data Filtering and HIPRO features may interfere with this.) Each
write to the Transmit FIFO contains 21 bits of address (A22-A2), 32 bits of data, and one
bit of interrupt information. The Transmit FIFO can hold up to 1024 writes before
becoming full.
When the Transmit FIFO reaches a FULL condition (CSR1[0] ON), one more host write
could cause a message to be lost. To prevent this, the CSR-controllable, built-in
S SC150e feature called HOLDOFF mode extends the computer write cycle
until the Transmit FIFO is able to empty at least one message.
2.3.2 Transceiver FIFO
The Transceiver buffer is used to receive foreign messages from the network, and send
them on, or to hold received foreign messages while inserting a native message from the
host onto the network.
Each node is responsible for receiving foreign messages, writing them to its copy of
shared memory, and re-transmitting the message to the next node.
2.3.3 Interrupt FIFO
The Interrupt FIFO contains a 21-bit address (A22 - A2) and a retry-status bit for each
shared-memory-based interrupt received. The Interrupt FIFO can hold 1024 interrupt
addresses. This FIFO can be read using CSR4 and CSR5.