Curtiss-Wright SCRAMNet+ SC150e Hardware Reference Manual Download

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INTRODUCTION

1-3

S SC150e HARDWARE REFERENCE

1.3 Quality Assurance

Curtiss-Wright Controls’ policy is to provide our customers with the highest quality

products and services. In addition to the physical product, the company provides

documentation, sales and marketing support, hardware and software technical support,

and timely product delivery. Our quality commitment begins with product concept, and

continues after receipt of the purchased product.
Curtiss-Wright Controls’ Quality System conforms to the ISO 9001 international standard

for

quality systems. ISO 9001 is the model for quality assurance in design, development,

production, installation, and servicing. The ISO 9001 standard addresses all 20 clauses of

the ISO quality system, and is the most comprehensive of the conformance standards.
Our Quality System addresses the following basic objectives:

•

Achieve, maintain, and continually improve the quality of our products through

established design, test, and production procedures.

•

Improve the quality of our operations to meet the needs of our customers,

suppliers, and other stakeholders.

•

Provide our employees with the tools and overall work environment to fulfill,

maintain, and improve product and service quality.

•

Ensure our customer and other stakeholders that only the highest quality product

or service will be delivered.

The British Standards Institution (BSI), the world’s largest and most respected

standardization authority, assessed Curtiss-Wright Controls’ Quality System. BSI’s

Quality Assurance division certified we meet or exceed all applicable international

standards, and issued Certificate of Registration, number FM 31468, on May 16, 1995.

The scope of Curtiss-Wright Controls’ registration is: “Design, manufacture and service

of high technology hardware and software computer communications products.” The

registration is maintained under BSI QA’s bi-annual quality audit program.
Customer feedback is integral to our quality and reliability program. We encourage

customers to contact us with questions, suggestions, or comments regarding any of our

products or services. We guarantee professional and quick responses to your questions,

comments, or problems.

Summary of Contents for SCRAMNet+ SC150e

Page 1: ...SC150e PCI PMC CPCI Bus Universal Signaling Hardware Reference Document No D T MR PCPMCPE A 1 A4 ...

Page 2: ......

Page 3: ...Net is a registered trademark of Curtiss Wright Controls Inc US Patent 4 928 289 ST is a registered trademark of AT T DIGITAL and DEC are trademarks of Digital Equipment Corporation PICMG and CompactPCI are registered trademarks of the PCI Industrial Computer Manufacturer s Group Curtiss Wright Controls Inc is an Associate Level member of PICMG and as such may use the PICMG and CompactPCI logos An...

Page 4: ...n which may interfere with other radio and communication devices The user may be in violation of FCC regulations if this device is used in other than the intended market environments CE As a component part of another system this product has no intrinsic function and is therefore not subject to the European Union CE EMC directive 89 336 EEC ...

Page 5: ...rupts 2 6 2 6 1 Network Interrupt Writes 2 6 2 6 2 Selected Interrupt 2 6 2 6 3 Forced Interrupt 2 8 2 7 External Triggers 2 9 2 8 General Purpose Counter Global Timer 2 9 2 9 Modes of Operation 2 9 2 9 1 Data Filter Mode 2 9 2 9 2 High Performance HIPRO Mode 2 10 2 9 3 Holdoff Mode 2 10 2 9 4 Loopback Modes 2 10 2 9 5 Write Me Last Mode 2 11 3 PRODUCT OVERVIEW 3 1 3 1 Overview 3 1 3 2 SCRAMNet SC...

Page 6: ...s 4 16 4 8 3 EEPROM Initialization 4 16 4 8 4 Node Identification 4 17 4 8 5 Network Time out 4 17 4 9 Byte Swapping 4 17 4 10 DMA Operation 4 18 4 11 Maintenance 4 18 4 12 Troubleshooting 4 18 5 OPERATION 5 1 5 1 Overview 5 1 5 2 Shared Memory 5 1 5 2 1 Virtual Paging 5 1 5 2 2 Memory Considerations 5 3 5 2 3 Control Status Registers 5 3 5 3 Initialization 5 4 5 4 Basic Send Receive Configuration...

Page 7: ...yout 4 4 Figure 4 4 CPCI Layout 4 5 Figure 4 5 EEPROM WRITE J303 4 6 Figure 4 6 EEPROM READ J304 4 6 Figure 4 7 PMC Card Installation 4 7 Figure 4 8 Fiber optic ST Connector 4 9 Figure 4 9 Fiber Optic Connections 4 10 Figure 4 10 Inserted State Power On 4 11 Figure 4 11 Bypass State Power Off 4 11 Figure 4 12 Inserted State Power On 4 12 Figure 4 13 Bypass State Power Off 4 13 Figure 4 14 Auxiliar...

Page 8: ...ons 4 17 Table 4 7 PCI_MAP0 PCI _MAP1 Swapping Options 4 17 Table 5 1 SCRAMNet SC150e Message Contents 5 5 Table 5 2 ACR Functions 5 8 Table 5 3 Interrupt Controls 5 10 Table 5 4 Interrupt Error Status Conditions 5 15 Table 5 5 General Purpose Counter Timer Modes 5 18 Table 5 6 Data Filter Options 5 19 Table 5 7 Monitor and Bypass Mode States 5 22 Table 5 8 Wire Loopback Mode States 5 23 Table 5 9...

Page 9: ...peration and of the specific host processor to use this manual effectively 1 1 3 Style Conventions Hexadecimal values are written with a 0x prefix For example 0x03FF Switch signal and jumper abbreviations are in capital letters For example RSW1 J5 etc Register bits and bit ranges are specified by the register identification followed by the bit or range of bits in brackets For example CSR6 4 CSR3 1...

Page 10: ...X and SCRAMNet SC150e hardware diagnostic software SCRAMNet SC150e EEPROM initialization software and the SCRAMNet Network Monitor SCRAMNet Network Media User s Guide Doc Nr D T MU MEDIA A description of network cabling hardware accessories for the SCRAMNet SC150e Network PCI Special Interest Group PCI SIG The PCI X specification is available to PCI SIG members and can be downloaded from www pcisi...

Page 11: ...on procedures Improve the quality of our operations to meet the needs of our customers suppliers and other stakeholders Provide our employees with the tools and overall work environment to fulfill maintain and improve product and service quality Ensure our customer and other stakeholders that only the highest quality product or service will be delivered The British Standards Institution BSI the wo...

Page 12: ...e this document comprehensive you may have specific problems or issues this document does not satisfactorily cover Our goal is to offer a combination of products and services that provide complete easy to use solutions for your application If you have any technical or non technical questions or comments contact us Hours of operation are from 8 00 a m to 5 00 p m Eastern Standard Daylight Time Phon...

Page 13: ...0e memory and system memory is any data written into SCRAMNet SC150e memory is automatically sent to the same SCRAMNet SC150e memory location in all nodes on the network This is why it is also referred to as replicated shared memory A good analogy is the COMMON AREA used by the FORTRAN programming language Where the COMMON AREA makes variables available to subroutines of a program SCRAMNet SC150e ...

Page 14: ...ENCE NODE IN NODE OUT Interrupt FIFO Transceiver FIFO Receiver Network Control Logic Transmitter Replicated Shared Memory Transmit FIFO Dual Port Memory Host Interface Logic All Reads All Reads All Writes ASIC Port 1 Host Port 2 Network P1 Figure 2 1 Functional Diagram ...

Page 15: ...ation of the node Refer to Figure 2 1 2 3 1 Transmit FIFO The Transmit FIFO is a message holding area for native messages waiting to be transmitted Each host write to SCRAMNet SC150e memory may constitute a write to the Transmit FIFO Data Filtering and HIPRO features may interfere with this Each write to the Transmit FIFO contains 21 bits of address A22 A2 32 bits of data and one bit of interrupt ...

Page 16: ... 62 µs Delay can be imposed when a node must complete the transmission of a native message packet before retransmitting a foreign message packet A SCRAMNet SC150e Network can accommodate up to 256 nodes per network ring 2 4 1 Protocol The protocol is a register insertion methodology and is NOT a token ring Depending on the protocol selected all message packets are the same size or are variable as ...

Page 17: ... it 0 1 Shared Memory ACR Memory CSR0 4 Host READ WRITE request to a specific 32 bit memory address Byte 0 Byte 1 Byte 2 Byte 3 Byte 0 PHYSICAL MEMORY CHIP DOES NOT REALLY EXIST LEGEND Figure 2 2 ACR Memory Access In Figure 2 2 host CPU read write operations are channeled to either SCRAMNet SC150e memory or to the ACR The ACR is a physically separate memory from the shared memory Channeling is bas...

Page 18: ...n Own Slot CSR2 10 are enabled the host has authorized a Self Interrupt The data is written to shared memory and the address is placed on the Interrupt FIFO Network Interrupt writes are accomplished by two methods Selected Data writes to selected shared memory locations from the network Forced Any data writes to any shared memory from the network In either case the node can be configured to write ...

Page 19: ...tions the following occurs The data is stored in that location The SCRAMNet SC150e address of the memory location is placed on the Interrupt FIFO queue and An interrupt is sent to the processor NETWORK ERRORS The Interrupt on Network Errors mode is enabled by setting CSR0 7 ON Network errors are defined in CSR1 according to an interrupt mask set in CSR9 When an incoming foreign message generates a...

Page 20: ...t method works the same for selected interrupt except for the choice of interrupt locations All shared memory locations are automatically set up to receive and or transmit interrupts depending on the ACR override conditions set in CSR0 6 and or CSR0 9 When Override Receive Interrupt Enable CSR0 6 is set an interrupt will be sent to the host by any network interrupt data message regardless of the s...

Page 21: ...all the global timers in the ring If the Trigger 2 event is the frame counter the timers in the ring effectively become synchronized sub frame timers which can then be used to tag time critical data or to measure and compare the completion time of various tasks within a distributed real time system 2 9 Modes of Operation 2 9 1 Data Filter Mode When SCRAMNet SC150e Data Filtering is enabled only th...

Page 22: ...en written through subsequent writes by the host CPU This can be accomplished by four consecutive 8 bit or two consecutive 16 bit writes to the SCRAMNet memory NOTE HIPRO WRITE will not work if Disable Host to Memory Write CSR2 8 is set or when writing two separate shortwords while using interrupts 2 9 3 Holdoff Mode It is possible that the Transmit FIFO can become full when the host is writing to...

Page 23: ...ptic Bypass Switch must be installed for this loopback to work However in the absence of the Fiber Optic Bypass Switch fiber optic cables could be run from the node s transmitter output connectors to the receiver input connectors This configuration with Insert Node enabled would constitute a Fiber optic Loopback mode for stand alone testing Set CSR2 6 ON to disable the Fiber optic Loopback mode wh...

Page 25: ...emory read operations bypass the SCRAMNet ASIC for improved performance Although both PIO and DMA operations are improved DMA operations will give the greatest increase in performance For PIO read operations the overall system performance is also improved as read latency is reduced the number of PCI retries is decreased and the PCI bus utilization is improved However the performance increase is li...

Page 26: ...aximum node separation of 3500 meters 3 2 2 SCRAMNet SC150e PMC Card Figure 3 2 SCRAMNet SC150e PMC Card The SCRAMNet SC150e PMC card offers the following features Card can be mounted on any PMC compliant carrier card in the computer chassis Designed in accordance with the PCI specification 2 1 32 bit PCI interface maximum bus speed of 33 MHz Uses the V363EPC PCI Bridge chip from QuickLogic Corp S...

Page 27: ...versal both 5 0 V and 3 3 V PCI signaling levels 2 MB 4 MB or 8 MB of on board shared memory 820 nm fiber optic interface maximum node separation of 300 meters 1300 nm fiber optic interface maximum node separation of 3500 meters Provides Basic Hot Swap capability in accordance with the CompactPCI Hot Swap Specification PICMG 2 1 R1 0 which allows Insertion of board into a powered system without ad...

Page 28: ...sary to establish the carrier 3 4 Software Contact Curtiss Wright Controls for availability of SCRAMNet SC150e diagnostic source code and software libraries 3 5 Utility Software 3 5 1 SCRAMNet Diagnostics The SCRAMNet Network Hardware Diagnostics are designed to test the functionality of the hardware This suite of tests automatically detects the type of card and adjusts the test menus accordingly ...

Page 29: ... the switch will not be illuminated during this state INSERTED MODE When a node is powered up the switch is automatically in the bypass state by default With power at the node the bypass switch is under software control By setting a bit in one of the SCRAMNet SC150e node s control registers the switch can be placed in the inserted mode The control signals are passed by an electrical connection bet...

Page 30: ... to four SCRAMNet nodes to be switched in or out of a primary SCRAMNet ring independently and dynamically Figure 3 5 It also allows sharing of a critical real time resource between multiple systems The Quad Switch performs other useful functions such as optical bypassing fiber optic repeating to gain transmission length beyond the SCRAMNet node s transmission power limit and to act as a media conv...

Page 31: ...isually LED s signify the state of node inclusion in the ring and if carrier is detected If the carrier is not detected the port is put into the Isolate state and the port is bypassed retaining ring integrity The auxiliary connector and the associated control cable links the port to the node allowing the application running the node to switch the Quad Switch in and out of Include or Isolate state ...

Page 33: ...atic environment Use an anti static mat connected to a wristband when handling or installing the SCRAMNet SC150e card 2 Open the anti static bag and remove the SCRAMNet SC150e card Save the shipping material in case the SCRAMNet SC150e card needs to be returned The optional fiber optic cables and Fiber Optic Bypass Switch are shipped in separate cartons 4 3 VisualIy Inspect the Card A label displa...

Page 38: ... header on the left pair of the write jumper as viewed from the fiber optic connector end of the card as shown in Figure 4 1 through Figure 4 3 Factory default ENABLED SET VERIFY EEPROM READ J304 J304 EEPROM READ ENABLE DISABLE Figure 4 6 EEPROM READ J304 To enable EEPROM READ install a 2 pin header on the left pair of the read jumper as viewed from the fiber optic connector end of the card as sho...

Page 39: ...t may result in serious damage to the host machine 1 Remove the bulkhead cover plate where the SCRAMNet SC150e host card will be 2 SC150e PMC only Mount the PMC card on a motherboard adapter or carrier card as shown in Figure 4 7 3 Slide the card into a desired peripheral bus slot while applying enough force to ensure a tight fit into the backplane connector After insertion use a standard Phillips...

Page 40: ...optic Configuration The SCRAMNet SC150e product is available in standard fiber optic media 820 nm wavelength for short distances and long link fiber optic media 1300 nm wavelength for long distances The part number label described in section 4 3 can be used to differentiate a SCRAMNet SC150e card with standard fiber optic media from a card with long link fiber optic media The basic SCRAMNet SC150e...

Page 41: ...ptional amount of light power loss experienced the cable ends should be inspected for cleanliness Alcohol based fiber optic cleaning pads are available to remove minor contaminants such as dust and dirt Figure 4 8 is a representation of a fiber optic connector Figure 4 8 Fiber optic ST Connector FIBER OPTIC CABLE PRECAUTIONS Fiber optic cables are made of glass and may break if crushed or bent in ...

Page 42: ... primary difference between the connector types is that the AT T connector provides a locking mechanism Before it can engage or disengage the blade on the card connection the plastic boot must be unscrewed at least inch and then re tightened The fiber optic cable pairs are connected between the transmitter pair of the down stream node and the receiver pair of the up stream node Continuing this typ...

Page 43: ...ion with SC150e PCI and CPCI Figure 4 10 and Figure 4 11 show the layout for the SCRAMNet SC150e PCI and CPCI which differs from the standard connection shown in Appendix A Figure A 2 Make Fiber Optic Bypass Switch connections as shown in Figure 4 10 and Figure 4 11 Figure 4 10 Inserted State Power On Figure 4 11 Bypass State Power Off ...

Page 44: ... in Figure 4 12 and Figure 4 13 Connect the 8 pin male DIN plug from the Fiber Optic Bypass Switch to the 8 pin female end of the PMC auxiliary connection cable Then connect the 3 pin female end of the PMC auxiliary connection cable to the auxiliary 3 pin male header of the PMC NOTE The PMC auxiliary connection cable is not provided with the bypass switch and must be purchased separately Contract ...

Page 46: ... Connection Table 4 1 PCI Auxiliary Connection Pinout Pins Name Definition 1 GND Logic Ground 2 N C No connection 3 F_RELAY Fiber optic Relay Drive and Sense 4 N C No connection 5 EXT_PWR 5 Source to External Ground 6 N C No connection 7 TRIGGER Trigger Output TRIG1 or TRIG2 8 N C No connection 4 7 4 Auxiliary Connection on SC150e PMC The Auxiliary Connection is used for communication with the Fib...

Page 47: ...Byte Offset Hex Alias Size Bytes Active Bits Type Register Description 1 2 CSR0 2 16 R W General SCRAMNet SC150e Enable and Reset 80 100 CSR1 2 16 R W SCRAMNet SC150e Error Indicators 103 206 CSR2 2 16 R W General SCRAMNet SC150e Control 182 304 CSR3 1 1 8 8 R W R W Number of nodes Node ID 205 40A CSR4 2 16 R Interrupt FIFO Address LSW 284 508 CSR5 2 9 7 R Interrupt FIFO Address MSW Reserved Write...

Page 48: ...5 where 000 CSR0 002 CSR1 004 CSR2 Both location 006 and 008 write to CSR3 TX_ID RX_ID This is possible because CSR4 is Read Only Then location 00A CSR5 etc Table 4 4 EEPROM Table 0 2 4 6 8 A C E 00 0000 0000 C040 XX00 XX00 0010 0000 0000 10 0800 0029 0001 0080 0000 0000 0000 0020 0000 0000 0000 0000 0000 0000 0000 0000 70 00B1 5300 0600 5555 006E 5555 5555 5555 NOTE XX denotes TX_ID and RX_ID Bot...

Page 49: ...ods of byte ordering Some have the byte order arranged from right to left Little Endian and others have the byte order going from left to right Big Endian Motorola is an example of a Big Endian system Intel is an example of a Little Endian system Table 4 6 is a simplified summary for 8 bit 16 bit and 32 bit byte ordering for big endian and little endian Table 4 6 Byte Ordering Comparisons Size Big...

Page 50: ...s the system will not boot up On UNIX like systems the driver generates a message on boot up similar to the following SCRAMNet installed and on line Problem Solution The boot up message does not appear The Register base address memory base address and or memory size may be incorrect NOTE All SCRAMNet SC150e nodes in the fiber optic network ring must be powered on unless they have Fiber Optic Bypas...

Page 51: ...e An example of a generic ISR is included in Figure 5 11 page 5 30 at the end of this section 5 2 Shared Memory Global variables are mapped directly onto the replicated shared memory The application program typically contains a list of variables or arrays which are stored in a contiguous space and which are to be shared across processors An analogy is a FORTRAN COMMON BLOCK For the purpose of iden...

Page 52: ...Node 1 Node 3 Node 5 Node 7 Node 9 Node 2 Node 4 Node 6 Node 8 4MB 4MB 2MB 2MB 2MB 2MB 1MB 1MB 8MB Network Address 7MB 5MB 3MB 1MB Figure 5 1 Memory Sharing With Virtual Paging To produce a network address the host write adds the relative SCRAMNet SC150e address and virtual page offset Relative address Virtual page offset Network address For example 12340 400000 412340 This network address is tran...

Page 53: ...multiple of the processor memory page size If this is not done most compilers will try to optimize memory usage by filling out the SCRAMNet SC150e memory pages with other data This can cause random results when this local data is transmitted around the network 5 2 3 Control Status Registers The SCRAMNet SC150e cards are controlled through CSRs for node status setting interrupt vectors setting inte...

Page 54: ... FIFOs Set CSR0 to 0x8003 to insert the node toggle the reset of the FIFOs and enable network activity Set CSR2 to 0xC040 to disable the Fiber optic Loopback mode Read CSR1 to read out any latched error conditions Read CSR1 again to check for any existing error conditions Check for carrier detect fail this means there are fiber optic cabling problems from the transmitter of the node downstream Wri...

Page 55: ...ONTROL BITS RES Reserved INT When this bit is set it signals an Interrupt Message RTY Retry message used only in error correction mode PLATINUM DATA ADDRESS This 21 bit A 22 2 field contains the relative SCRAMNet SC150e memory address Bits A0 and A1 are always zero for a longword boundary DATA VALUE This 32 bit field contains the data value in SCRAMNet SC150e memory that is currently being updated...

Page 56: ...ode appends 4 byte data values with sequential addresses until the maximum of 256 or 1024 bytes is reached a non sequential address is detected the Transmit FIFO is empty or a transmit interrupt event is detected In both BURST and PLATINUM modes the node is permitted to have multiple packets on the ring simultaneously The transmission of a PLUS mode message is an automatic function and for the mos...

Page 57: ...ssage can be retransmitted This delay is a minimum of 247 ns the time to transmit one byte The maximum node latency depends on the maximum message size and could be from 800 ns to 61 8 µs depending on the message length selection To approximate the total maximum delay on the network multiply the maximum node latency by the number of nodes in the system and add a propagation delay of 5 ns meter mul...

Page 58: ...it FIFO In PLATINUM and PLATINUM PLUS modes error detection is enabled This will affect node latency in that some messages must be retransmitted NETWORK TIME OUT Reset the transmit time out according to the mode of operation selected by writing a 16 bit non zero value to CSR5 as described in subsection 4 8 4 5 6 Auxiliary Control RAM The ACR is a 5 bit register When ACR Enable CSR0 4 is set shared...

Page 59: ...or interrupts from memory writes Receive and or Transmit CSR0 1 0 must be enabled in order for the node to receive and or transmit network data There are other combinations of CSR settings to achieve varied interrupt results Appendix B CSR DESCRIPTIONS describes the SCRAMNet SC150e CSRs in detail In order for the HIPRO mode to become active ACR 4 must be set for those selected memory addresses whe...

Page 60: ...enerates an interrupt request as specified in the CSR9 Mask register as the corresponding bit in CSR1 is set Network Interrupt Enable CSR0 8 Permits transmission of interrupt data to the network Override TIE CSR0 9 Transmits Interrupt message to the network regardless of the ACR TIE setting Reset Interrupt FIFO CSR0 13 Toggle from 0 to 1 to 0 to reset Interrupt FIFO Interrupts Armed CSR1 14 During...

Page 61: ...interrupt on errors 5 8 Interrupt Conditions Interrupts are generated under two different conditions A SCRAMNet SC150e network data write to shared memory A SCRAMNet SC150e network error detected on the local node 5 8 1 Network Data Write As indicated in Figure 5 2 the Transmit Enable CSR0 1 must be set before any message can be sent Only those nodes which have the Transmit Interrupt Enable ACR 1 ...

Page 62: ... REFERENCE ACR TIE HOST WRITE OVERRIDE TIE NETWORK INTERRUPT ENABLE TRANSMIT INTERRUPT SLOT TO NETWORK TRANSMIT NON INTERRUPT SLOT TO NETWORK CSR0 9 CSR0 8 NO NO ACR 1 YES YES YES NO TRANSMIT ENABLE CSR0 1 MUST BE ACTIVE Figure 5 2 Transmit Interrupt Logic ...

Page 63: ...terrupts This allows the message with the interrupt bit set to be processed as an incoming network interrupt CSR2 9 enables the node s own message to be received as a network message CSR2 10 allows the interrupt bit to generate an interrupt if it is set SELF INTERRUPTS Set CSR2 10 9 to enable self interrupts This allows the message with the interrupt bit set to be processed as an incoming network ...

Page 64: ...NERATE INTERRUPT TO HOST NO INTERRUPT TO HOST PLACE ADDRESS INTO INTERRUPT FIFO NO INTERRUPT TO HOST CSR1 NETWORK ERROR MESSAGE PACKET NATIVE MSG ERROR MASK BIT SET CSR9 RECEIVE INT OVERRIDE INTERRUPT MESSAGE NO NO YES YES NO NO YES YES YES NO NO NO YES YES CSR8 10 OVERRIDE RIE ENB INT ON Rx IN OWN SLOT WRITE OWN SLOT ENB NO YES YES NO NO RECEIVE ENABLE CSR0 0 MUST BE ACTIVE YES NO YES Figure 5 3 ...

Page 65: ...it being set value 1 in CSR1 If any of the preceding conditions are set and the Interrupt On Memory Mask Match Enable CSR0 5 is set then an interrupt will be generated to the host computer Additional information about each error condition is contained in appendix B Table B 2 CSR1 If a Network Error is received Figure 5 3 and if Interrupt on Error CSR0 7 and Host Interrupt Enable CSR0 3 are set and...

Page 66: ...rrupt address When an interrupt is received the ISR should read CSR5 first in order to check the Interrupt FIFO Not Empty bit If this bit is set value is 1 then read CSR4 If this bit is CLEAR value is 0 then the Interrupt FIFO is empty Therefore the interrupt was due to an error assuming that Enable Interrupt On Error is set Every read from CSR5 and CSR4 will contain the SCRAMNet SC150e memory add...

Page 67: ...A and enable trigger 1 by setting ACR 2 and not ACR 3 2 Select the same memory address in node B and enable trigger 2 by setting ACR 3 and not ACR 2 3 Connect a wire from TRIG1 to an oscilloscope 4 Connect a wire from TRIG2 to the oscilloscope 5 Initiate a HOST write to the node A memory address When the corresponding NETWORK write occurs the time difference can be measured EXAMPLE 2 MEASURE RING ...

Page 68: ...urs the counter will increment Transit Time Set this mode and clear the counter The counter will begin counting when the next message is transmitted and stop counting when any message generated by this node is received Network Events Count incoming network messages Free Run 26 66 ns Increment counter using internal 37 5 MHz clock Counter will roll over every 1 78 ms Free Run 1 706 μs with Trigger ...

Page 69: ...that have not actually changed In order to reduce network traffic the SCRAMNet SC150e card has the ability to compare the new value with the old value of data and avoid sending unchanged data values out on the network This feature is a type of data filtering and can be enabled without affecting node latency while improving network throughput See Figure 5 4 Data Filter Logic CSR0 10 and CSR0 11 con...

Page 70: ...007 5 20 SCRAMNet SC150e HARDWARE REFERENCE DATA FILTER LOGIC DO NOTHING YES SAME WRITE TO MEMORY NEW DATUM OLD DATUM NO READ WRITE HOST CPU NETWORK RING NETWORK RING SHARED MEMORY NETWORK LOGIC Figure 5 4 Data Filter Logic ...

Page 71: ...st shortword write is initiated or a total of 4 byte writes if a byte write is initiated to a HIPRO location Otherwise it is possible to partially write a 32 bit location causing the data to be lost and never be transmitted The HIPRO mode is also effective for transmitting user defined 16 bit data items Two 16 bit data items may be sent as one 32 bit data item if they are consecutive and lie withi...

Page 72: ...nd Bypass Mode States State Register Setting Receive Enable CSR0 0 ON Transmit Enable CSR0 1 DON T CARE Insert Enable CSR0 15 OFF Enable Wire Loopback CSR2 7 OFF Media Circuitry Rx Tx Rx Tx Internal PLL and Data Recovery MECHSWITCH FO Conv FO Conv Fiber Optic Bypass Switch Optional RX ENABLE TX ENABLE OFF ON OFF ON OFF ON OFF ON INSERT ENABLE WIRE LOOPBACK Figure 5 5 Monitor and Bypass Mode ...

Page 73: ... signal does not leave the card Table 5 8 Wire Loopback Mode States State Register Setting Receive Enable CSR0 0 ON Transmit Enable CSR0 1 ON Insert Enable CSR0 15 OFF Enable Wire Loopback CSR2 7 ON Media Circuitry Rx Tx Rx Tx Internal PLL and Data Recovery MECHSWITCH FO Conv FO Conv Fiber Optic Bypass Switch Optional RX ENABLE TX ENABLE OFF ON OFF ON OFF ON OFF ON ENABLE WIRE LOOPBACK INSERT Figu...

Page 74: ...pback Mode States State Register Setting Receive Enable CSR0 0 ON Transmit Enable CSR0 1 ON Insert Enable CSR0 15 ON Enable Wire Loopback CSR2 7 OFF Mechanical Switch Override CSR8 11 OFF Media Circuitry Rx Tx Rx Tx Internal PLL and Data Recovery MECHSWITCH FO Conv FO Conv Fiber Optic Bypass Switch Optional RX ENABLE TX ENABLE OFF ON OFF ON OFF ON OFF ON ENABLE WIRE LOOPBACK INSERT Figure 5 7 Mech...

Page 75: ...ber optic Loopback Mode States State Register Setting Receive Enable CSR0 0 ON Transmit Enable CSR0 1 ON Insert Enable CSR0 15 ON Enable Wire Loopback CSR2 7 OFF Disable Fiber optic Loopback CSR2 6 OFF Mechanical Switch Override CSR8 11 ON Media Circuitry Rx Tx Rx Tx Internal PLL and Data Recovery MECHSWITCH FO Conv FO Conv Fiber Optic Bypass Switch Optional RX ENABLE TX ENABLE OFF ON OFF ON OFF O...

Page 76: ...bling Loopback mode To disable the Fiber optic Loopback mode set CSR2 6 ON This state allows data to be transmitted and received on the network ring for this node When the Fiber optic Loopback mode is enabled CSR2 6 OFF the Fiber Optic Bypass Switch prevents the node from receiving network data Likewise the node cannot transmit any data into the network ring When power is lost to the Fiber Optic B...

Page 77: ...smit FIFO becomes full The Transmit FIFO serves as a buffer between the SCRAMNet SC150e memory and the SCRAMNet SC150e network The Transmit FIFO can become full when the host CPU is writing to SCRAMNet SC150e memory faster than the network can absorb the data If a CPU is capable of writing to the SCRAMNet SC150e memory on the PCI bus at such a rate that the Transmit FIFO becomes full 1024 deep dat...

Page 78: ...ly configure active SCRAMNet and SCRAMNet SC150e ring s The Quad Switch provides dynamic configuration of up to five separate rings Each separate ring is connected to a port on the Quad Switch Refer to Figure 5 10 Each ring can be isolated from the other rings or can be included with one or more of the other attached rings There is a single logical ring internal to the Quad Switch The Quad Switch ...

Page 80: ...ic then the Interrupt Service Routine will be invoked Interrupts will be disabled until re armed by writing to CSR1 Until that time all other interrupts will be written into the Interrupt FIFO where they can be processed in the Interrupt Service Routine If Interrupts on Errors is enabled then an interrupt due to an error has occurred if the interrupt FIFO is empty on the initial check of CSR5 in t...

Page 81: ...rd Dimensions A 2 A 2 SC150e PMC A 3 A 2 1 Hardware Specifications A 3 A 2 2 Card Dimensions A 4 A 3 SC150e CPCI A 5 A 3 1 Hardware Specifications A 5 A 3 2 Card Dimensions A 6 A 4 Performance A 7 A 5 Part Number A 7 A 6 Fiber Optic Cables A 8 A 7 Fiber Optic Bypass Switch A 9 A 7 1 Fiber Optic Bypass Switch Dimensions A 10 ...

Page 82: ......

Page 83: ...installed memory options 2 MB 4 MB or 8 MB Effective Per Node Bandwidth 4 bytes packet 6 5 MB sec 256 bytes packet 16 2 MB sec 1024 bytes packet 16 7 MB sec Node Latency 4 bytes packet 250 ns 800 ns 256 bytes packet 250 ns 16 µs 1024 bytes packet 250 ns 61 8 µs Mean Time Between Failures MTBF 2 MB Memory 231 748 hours 4 MB Memory 217 808 hours 8 MB Memory 186 721 hours Internal clock speeds SCRAMN...

Page 85: ...Maximum Node Separation Standard Fiber 300 meters Long Link Fiber 3500 meters Factory installed memory options 2 MB 4 MB or 8 MB Effective Per Node Bandwidth 4 bytes packet 6 5 MB sec 256 bytes packet 16 2 MB sec 1024 bytes packet 16 7 MB sec Node Latency 4 bytes packet 250 ns 800 ns 256 bytes packet 250 ns 16 µs 1024 bytes packet 250 ns 61 8 µs Mean Time Between Failures MTBF 2 MB Memory 225 361 ...

Page 87: ... Factory installed memory options 2 MB 4 MB or 8 MB Effective Per Node Bandwidth 4 bytes packet 6 5 MB sec 256 bytes packet 16 2 MB sec 1024 bytes packet 16 7 MB sec Node Latency 4 bytes packet 250 ns 800 ns 256 bytes packet 250 ns 16 µs 1024 bytes packet 250 ns 61 8 µs Mean Time Between Failures MTBF 2 MB Memory 187 887 hours 4 MB Memory 187 740 hours 8 MB Memory 185 809 hours Internal clock spee...

Page 89: ...ng ON and DEC_IGNORE OFF 13 3 16 1 13 3 8 7 1 Results derived from a software test using a time stamp counter 2 By default this product is configured with prefetching enabled Refer to V363EPC User Manual for details of prefetching operation including possible data coherency issues 3 Host limited A 5 Part Number The PCI Card part number is in the form H AS DPCIG02M 20 Standard PCI w 2 MB RAM H AS D...

Page 90: ...bility of fiber optic cables The part number for Curtiss Wright Controls 62 5 125 micron fiber optic cables is in the form H PR WST23000 0 paired 62 5 125 micron cable 3 meters where Code Definition H Hardware PR Part WST2 Standard Fiber Commercial Grade Cable Paired 62 5 micron core multi mode fiber optic cable XXXX Length of cable examples 3000 3 meter cable 5000 5 meter cable 1001 10 meter cabl...

Page 93: ...NLY B 8 Table B 5 CSR4 Interrupt Address LSP READ ONLY B 8 Table B 6 CSR5 Interrupt Address and Status READ ONLY B 8 Table B 7 CSR6 Reserved B 9 Table B 8 CSR7 Reserved B 9 Table B 9 CSR8 General SCRAMNet SC150e Extended Control Register B 9 Table B 10 CSR9 SCRAMNet SC150e Interrupt On Error Mask B 10 Table B 11 CSR10 DEC_IGNORE B 10 Table B 12 CSR11 Reserved B 11 Table B 13 CSR12 SCRAMNet SC150e ...

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Page 95: ...egister and the function of each bit The name of each bit is indicative of its set state The registers are described using bit 0 as the Least Significant Bit LSB For example Inserting 0xA7C3 in a 16 bit register would set bits 0 1 6 7 8 9 10 13 and 15 ON 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 0 0 1 1 1 1 1 0 0 0 0 1 1 A 7 C 3 ...

Page 96: ...When this bit is cycled 0 1 0 the optional redundant transceiver selected link is changed 3 Host Interrupt Enable When this bit is set a received message that is written to node shared memory as an interrupt will generate an interrupt request and the address will be written to the Interrupt FIFO This bit must be set in order to receive any interrupts from the network 4 Auxiliary Control RAM Enable...

Page 97: ...ive Transmit FIFO This bit must be toggled from 0 to 1 and back to 0 in order to reset the Receive Transmit FIFO The R T FIFO is a temporary high speed holding area for data flowing through the network NOTE If the R T FIFO were to be reset during active network transmissions the data in the FIFO at that time would be lost and it would cause errors on the downstream nodes in the network ring 13 Res...

Page 98: ...his bit is set if the receivers do not detect any or enough output from the previous nodes transmitters This is usually an indication that the fiber optic lines have become disconnected or there may be dust dirt where the fiber optic connections have been made A visual inspection of the network lines will need to be made 7 Bad Message Latched When this bit is set the hardware has detected an error...

Page 99: ...conditions to receive an interrupt are active If this bit is 0 then the host will receive no interrupts When CSR1 is written to then the interrupts armed bit will return to an active status 15 Fiber Optic Bypass Not Connected This is a status bit concerning the installation of the optional Fiber Optic Bypass Switch A 0 in this bit indicates that the bypass switch is installed while a 1 indicates i...

Page 100: ... but may be used in conjunction with CSR2 10 when it is desired to generate an interrupt to the host written by the host 10 Enable Interrupt On Own Slot When this bit is set a message with the interrupt bit set can be received by the originating node if CSR2 9 is also set This coupling enables a host processor to interrupt itself Self Interrupt 11 Message Length Limit Variable maximum message size...

Page 101: ... 14 to enable communication protocols BURST or PLATINUM mode and the variable length message PLUS mode see below SCRAMNet SC150e Protocol Mode Definition CSR2 15 CSR2 14 CSR2 12 CSR2 11 Network Mode No Error Correction Multiple Message Variable Length Message Size Maximum BURST 1 1 0 NO MEANING PLATINUM 0 1 0 NO MEANING BURST 1 1 1 1 1024 0 256 PLATINUM 0 1 1 1 1024 0 256 ...

Page 102: ... LSP READ ONLY Bits Description 15 0 LSP of the Interrupt Address These bits represent the LSP of the interrupt address A15 A0 Bits 0 and 1 are always 0 since the addresses are on four byte boundaries Table B 6 CSR5 Interrupt Address and Status READ ONLY Bits Description 6 0 MSP of the Interrupt Address These 7 bits represent the MSP of the interrupt address A22 A16 When coupled with CSR4 this add...

Page 103: ...ose Counter Timer Free Run Setting this bit causes the GPC to free run at a rate of 37 5 MHz 26 66 ns This counter mode overrides all other counter mode settings 10 Receive Interrupt Override When this bit is set all incoming network messages are treated as interrupt messages 11 Mechanical Switch Override Normally set to ON When OFF Mechanical Switch Loopback Mode is invoked 14 12 Memory Size Conf...

Page 104: ...Retry Due to Time Out Mask 11 Redundant TX RX Fault Mask 12 Interrupt on General Purpose Counter Timer Overflow Mask 13 See Below 14 See Below 15 Fiber Optic Bypass Switch Not Connected Mask General Purpose Counter Timer Modes CSR8 9 CSR9 14 CSR9 13 Counter Timer Modes 0 0 0 Count Errors 0 0 1 Count Trigs 1 2 0 1 0 Transit Time 0 1 1 Network Events 1 1 X Free Run 26 66 ns 1 0 1 1 706 µs w trig 2 C...

Page 105: ...ng Register Bits Description 0 VP Virtual Paging Enable When ON this bit enables Virtual Paging 4 1 0 Always zero 5 VP_A12 6 VP_A13 7 VP_A14 8 VP_A15 9 VP_A16 10 VP_A17 11 VP_A18 12 VP_A19 13 VP_A20 14 VP_A21 15 VP_A22 Virtual Page number The significance of this register is dependent on the memory size For example For 4 MB only VP_A22 is valid for 4 KB P_A 22 12 are valid ...

Page 106: ... RD_COUNT 6 This is a General Purpose Counter Timer register It can be used to 7 RD_COUNT 7 count trigger 1 and 2 events count errors or other events as 8 RD_COUNT 8 programmed by CSR9 13 and CSR9 14 9 RD_COUNT 9 10 RD_COUNT 10 11 RD_COUNT 11 12 RD_COUNT 12 13 RD_COUNT 13 14 RD_COUNT 14 15 RD_COUNT 15 Table B 15 CSR14 Reserved Bits Description 15 0 Not Used Table B 16 CSR15 Reserved Bits Descripti...

Page 107: ... Address MSW and Status READ Only C 6 C 7 CSR6 Reserved C 6 C 8 CSR7 Reserved C 6 C 9 CSR8 General SCRAMNet SC150e Extended Control Register C 7 C 10 CSR9 SCRAMNet SC150e Interrupt On Error Mask C 8 C 11 CSR10 DEC_IGNORE C 9 C 12 CSR11 Reserved C 9 C 13 CSR12 SCRAMNet SC150e Virtual Paging Register C 10 C 14 CSR13 SCRAMNet SC150e General Purpose Counter Timer C 10 C 15 CSR14 Reserved C 11 C 16 CSR...

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Page 109: ...ggle RTT 3 Host Interrupt Enable HIE 4 Auxiliary Control RAM Enable ACRE 5 Interrupt on Memory Mask Match Enable IMME 6 Override RIE Flag ORF 7 Interrupt on Errors IOE 8 Network Interrupt Enable NIE 9 Override TIE Flag OTF 10 Enable Tx Data Filter DFEN 11 Enable Lower 4 Kbytes for Data Filter EN4K 12 RESET Rx Tx FIFO RTRF 13 RESET Interrupt FIFO RSTIF 14 RESET Transmit FIFO RTXF 15 Insert Node INS...

Page 110: ... TXFAF 3 Always 0 Not Used 4 Interrupt FIFO Full IFF 5 Protocol Violation PV 6 Carrier Detect Failure CDF 7 Bad Message BB 8 Receiver Overflow RXO 9 Transmit Retry TXRTY 10 Transmit Retry Time out TO 11 Redundant TxRx Fault RTF 12 General Purpose Counter Timer Overflow GPCTO 13 Redundant TxRx Link 1 A 0 B RTLAB 14 Interrupts Armed Write to re arm IARM 15 Fiber Optic Bypass Not Connected FOB ...

Page 111: ...12 Variable length messages on network VAR_LEN 13 HIPRO Write Enable HIPRO 14 Allow multiple native messages on network MULTIPLE_MSG 15 No Network Error Correction NO_ERR_CRCT Write Me Last Self Interrupt Mode Definition CSR2 10 CSR2 9 CSR2 8 Mode 0 1 1 WRITE ME LAST mode 1 1 0 SELF INTERRUPT mode 1 1 1 WRITE ME LAST with SELF INTERRUPT mode SCRAMNet Protocol Mode Definition CSR2 15 CSR2 14 CSR2 1...

Page 112: ...rmation Bit Function Name 0 NN0 1 NN1 2 NN2 3 Node Number Count NN3 4 Valid After a Transmission from the Node NN4 5 NN5 6 NN6 7 NN7 8 NID0 9 NID1 10 NID2 11 Node ID Number NID3 12 NID4 13 NID5 14 NID6 15 NID7 When ID_MUX CSR 0 is set Bits 7 0 are Transmit AGE Bits 15 8 are Receive ID ...

Page 113: ... SC150e HARDWARE REFERENCE C 5 CSR4 Interrupt Address LSW Bit Function Name 0 Always 0 1 Always 0 2 RFA2 3 RFA3 4 RFA4 5 RFA5 6 Interrupt FIFO Address Field LSW RFA6 7 RFA7 8 RFA8 9 RFA9 10 RFA10 11 RFA11 12 RFA12 13 RFA13 14 RFA14 15 RFA15 ...

Page 114: ...A22 13 7 Reserved 0 14 Retry Bit in Interrupt FIFO RF_RETRY 15 Interrupt FIFO Not Empty RX_F_E Writing the Transmit Time out value to CSR5 stores it in shadow memory Do not set this value to 0 A value of 0 prevents host generated data from leaving the Transmit FIFO C 7 CSR6 Reserved A 16 bit Read Only Curtiss Wright Controls reserved register C 8 CSR7 Reserved A 16 bit Read Only Curtiss Wright Con...

Page 115: ...ine to MICROWIRE port CSR_CK 7 DIN line connected to the MICROWIRE DOUT pins E_DIN 8 Initiate initiation sequence CSR Reset CSR_RST 9 Override Counter mode GPC_FRE 10 Receive Interrupt Override RX_INT_OVR 11 1 Mechanical Switch Override C_MECHSW 0 Invoke Coax Loopback Mode 12 Memory Size Configuration See below MC10 13 Memory Size Configuration See below MC11 14 Memory Size Configuration See below...

Page 116: ...Message mask M_BM 8 Receiver Overflow mask M_RX_OVR 9 Transmitter Retry mask M_RETRY 10 Transmitter Retry Time out M_RETRY_T_O 11 Redundant Transmit Receive Fault mask M_FAULT 12 Interrupt on Utility Counter Overflow M_COUNT_OVR 13 General Purpose Counter Timer Modes See below M_INC_TRIGS 14 General Purpose Counter Timer Modes See below M_INC_ERRS 15 Fiber Optic Bypass Not Connected mask M_FO_BYPA...

Page 117: ...2007 C 9 SCRAMNet SC150e HARDWARE REFERENCE C 11 CSR10 DEC_IGNORE Bit Function Name 0 1 Non DEC system 0 DEC system DEC_IGNORE 15 1 Reserved 0 C 12 CSR11 Reserved A 16 bit Read Only Curtiss Wright Controls reserved register ...

Page 118: ... 5 subsection 5 10 and Appendix B page B 12 for additional information Bit Function Name 0 Counter Timer register RD_COUNT 0 1 Counter Timer register RD_COUNT 1 2 Counter Timer register RD_COUNT 2 3 Counter Timer register RD_COUNT 3 4 Counter Timer register RD_COUNT 4 5 Counter Timer register RD_COUNT 5 6 Counter Timer register RD_COUNT 6 7 Counter Timer register RD_COUNT 7 8 Counter Timer registe...

Page 119: ...eserved A 16 bit Read Only Curtiss Wright Controls reserved register C 17 Auxiliary Control RAM R W Bit Function Name 0 Receive Interrupt Enable RIE 1 Transmit Interrupt Enable TIE 2 External Trigger 1 Host Read Write ET1 3 External Trigger 2 Network Write ET2 4 HIPRO HIPRO 7 5 Reserved 0 User access to Trigger 1 and Trigger 2 is not available on the PMC Card ...

Page 121: ...D D CONFIGURATION AIDS APPENDIX D CONFIGURATION AIDS ...

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Page 123: ...4 15 reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved ACR LED STATUS 0 1 2 3 RIE TIE EXT TRG 1 EXT TRG 2 4 5 6 7 HIPRO ENB reserved reserved reserved G G INSERT CARRIER DETECT CSR 1 READ RESET CSR 3 CSR 5 CSR 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TX FIFO FULL TX FIFO NOT EMPTY TX FIFO 7 8 FULL Always 0...

Page 124: ...erved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved CSR 9 CSR 11 CSR 13 CSR 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TX FIFO FULL MASK TX FIFO NOT EMP MASK TX FIFO 7 8 FULL MASK BIST STREAM R O RX FIFO FULL MASK PROTOCOL VIOL MASK CARRIER DETECT FAIL MASK BAD MESSAGE MASK RX OVERFLOW MASK TX RETRY MASK TX RETRY TIME OUT REDUN TXRX FAULT MASK GP CTR TIMER...

Page 125: ...RATION AIDS Copyright 2007 D 3 SCRAMNet SC150e HARDWARE REFERENCE SCRAMNet SC150e NETWORK CONFIGURATION DATA SHEET NODE ID HOST MACHINE MEMORY ADDRESS BUS MEMORY SIZE CSR ADDRESS BUS INT LEVEL SCRAMNet SERIAL ...

Page 127: ...1 GLOSSARY GLOSSARY ...

Page 128: ......

Page 129: ...ch transfer so that the data for the next cycle is retrieved from the next higher location block write cycle A DTB cycle used to transfer a block of 1 to 256 bytes from a master to a slave The block write cycle is very similar to the block read cycle It uses a string of 1 2 or 4 byte data transfers and the master does not release the DTB until all of the bytes have been transferred It differs from...

Page 130: ... direct memory access DMA transfer An I O transfer conducted by a device controller which accesses memory directly and as a result can transfer a large volume of data without requesting a processor interrupt after each unit amount Contrast with programmed I O PIO transfer DTB A mnemonic for data transfer bus edges Transitions that appear on a signal line EEPROM The EEPROM stores the initial power ...

Page 131: ...etween itself and a slave module message packet See packet native message A message that is received by the node of origin node latency The time delay at a node before a foreign message can be retransmitted packet A message that travels on the network The minimum packet consists of 81 bits and 1 start bit The packet includes five fields Source ID 8 bits Age 8 bits Control 3 bits Data Address 21 bi...

Page 132: ...ror The originating node will retransmit the message indefinitely until the originating node receives it correctly Valid only in error correction mode PLATINUM retry time out A hardware failure condition reported when the first attempt to send a message around the network is not received by the originating node within the time out period specified in CSR5 The originating node will retransmit the m...

Page 133: ... bus time out Also network time out The time written to CSR5 that must elapse before a native message will be retransmitted The time out must be a non zero value Tx Abbreviation for transmit or transmitter UAT A master that sends or receives data in an unaligned fashion utility bus One of the four buses provided by the backplane This bus includes signals that provide periodic timing and coordinate...

Page 135: ...1 INDEX INDEX ...

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Page 137: ...enable lower 4 KB B 3 DEC_IGNORE setting 4 1 4 16 DEC_IGNORE setting A 7 B 10 C 9 D 2 E EEPROM initialization 1 2 4 16 5 4 read enable 4 6 write enable 4 6 EEPROM program enable C 7 electrical requirements A 1 A 3 A 5 error conditions 2 7 5 3 5 4 5 11 5 15 bad message 5 15 B 3 B 4 C 2 C 8 carrier detect B 4 carrier detect fail 5 15 C 2 C 8 FOBS not connected 5 15 interrupt FIFO full B 3 latched B ...

Page 138: ...r loss 4 9 little endian 4 17 longword address 5 16 longword addresses 2 5 M memory address 2 1 5 1 5 2 5 4 5 5 5 16 5 17 5 21 B 9 selected 5 9 message packet contents 5 5 fixed length 2 4 5 5 A 1 A 3 A 5 foreign 2 3 2 4 2 7 5 7 maximum size 2 5 native 2 3 2 4 5 13 variable length B 6 C 3 variable length maximum B 6 variable length 2 4 A 1 A 3 A 5 B 7 C 3 message packet size 2 4 message packets co...

Page 139: ...rface address 3 7 serial port interface 3 7 single logical ring internal 5 28 R read latency 3 1 receive interrupt override B 9 C 7 receive interrupt enable flag C 1 receive transmit FIFO B 3 reset B 3 receiver FIFO 2 4 full C 8 receiver overflow mask B 10 redundant transceiver B 2 C 1 C 2 fault C 2 fault mask B 10 register shadow 4 17 register virtual paging 4 15 register insertion 2 4 registers ...

Page 140: ...y B 4 B 10 C 2 C 8 reset B 3 C 1 transmit interrupt enable flag C 1 transmitter retry mask B 10 C 8 time out C 8 transmitter retry time out mask B 10 U utility EEPROM initialization program 3 4 hardware diagnostic 3 4 Monitor program 3 4 V virtual page number B 11 virtual paging B 11 C 10 enable 5 1 B 11 W weight A 1 A 3 A 5 wire loopback enable B 3 B 6 C 3 internal circuitry 5 23 write own slot e...

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