Curtiss-Wright SCRAMNet+ SC150 VME6U, Hardware Reference Manual, Page: 56 / 162

OPERATION
Copyright 2007 5-8 VME6U HARDWARE REFERENCE
5.6 Auxiliary Control RAM
The ACR is an 8-bit register. However, only ACR[4:0] are implemented. ACR[7:5] are
not defined.
When ACR Enable CSR0[4] is set, shared memory is not accessible by the host, and the
ACR byte is viewed as the least significant byte of every shared-memory four-byte
address. The ACR byte value controls the external trigger and/or interrupt action(s) taken
whenever a WRITE occurs to any byte of the shared-memory 4-byte word. Table 5-2
describes the ACR functions.
If these ACR actions are disabled, then no action will be taken when an interrupt
condition exists unless override bits CSR0[6] or CSR8[10] are set.
The external trigger and/or interrupt action and/or HIPRO mode for a particular shared-
memory location is defined by setting these bits. Once the ACR has been defined, set
ACR Enable bit CSR0[4] back to zero so that shared memory can again be accessed. The
ACR actions are still in effect, but the ACR bytes can no longer be accessed while the
ACR Enable bit is zero.
Table 5-2 ACR Functions
Bit Function
0 Receive Interrupt Enable (RIE)
1 Transmit Interrupt Enable (TIE)
2 External Trigger 1
3 External Trigger 2
4 HIPRO Location Enable
7-5 Reserved
In order for the ACR values to take effect for interrupt action, the following
SCRAMNet
+
CSR actions should be considered for the type of interrupt operation
desired:
•
Host Interrupt Enable CSR0[3] to receive network interrupts
•
Network Interrupt Enable CSR0[8] to transmit network interrupts
•
Interrupt on Memory Mask Match Enable CSR0[5] for interrupts from memory
WRITEs
Receive and/or Transmit CSR0[1:0] must be enabled in order for the node to receive
and/or transmit network data. There are other combinations of CSR settings to achieve
varied interrupt results. Section 5 describes the SCRAMNet
+
CSRs in detail.
In order for the external triggers 1 and 2 to take place, ACR[2] and ACR[3], respectively,
must be set. In order for the HIPRO mode to become active, ACR[4] must be set for
those selected memory addresses where this is to occur. Additionally, CSR2[13] must be
set to enable the HIPRO mode. All five of the defined bits of the ACR can be used in any
combination to achieve varied results for any shared-memory location.