Curtiss-Wright SCRAMNet+ SC150 VME6U, Hardware Reference Manual, Page: 138 / 162

HOST ACCESS TIMING
Copyright 2007 E-6 VME6U HARDWARE REFERENCE
E.4.1 Host-Specific CSR READ
READ operations on the external CSRs do not go through normal ASIC data paths.
Therefore, timings for this cycle vary from other CSR READ cycles. These external
CSRs are not ASIC resources and therefore do not request ASIC cycles to READ from
them. Additional host logic monitors host access to these locations, and CSR data is
provided directly to the host CPU without performing an ASIC Host Request (HREQ).
The following is the general format of an external CSR READ cycle:
AS and DS asserted
Additional host captures request
Provides READ data
Asserts DTACK
Requester (Master/CPU) de-asserts AS and DS
Figure E-5 is an example of a READ from an external CSR.
DTACK*
AS*
DSx*
HREQ
HACK
1
2
1. AS to DSx = 10 ns (per VME Spec.)
2. DSx to DTACK = 186 ns (Host Adapter time)
3. DTACK to End of Cycle = 0 ns (per VME Spec.) 196 ns
NOTE: There is no Host Request (HREQ) because this is not an ASIC resource
Figure E-5 READ From External CSR
E.5 Access Times
Host access to shared memory is affected by two things:
Priority on contention between the two ports
Asynchronous request handling
There are minimum and maximum times that depend on Network WRITE priority and
the asynchronous handling of the requests. The minimum DPRC access times (i.e., no
contention between ports) are shown in Table E-1. This table does not include host
timing. The “worst case” scenario resulting in maximum access times would be a host
WRITE followed immediately by another host WRITE, and simultaneous receipt of three
network WRITES.
Minimum access times occur when there is no contention. Maximum access times result
when the worst possible case of contention occurs.
The SCRAMNet
+
cycle is initiated by the assertion of the DS and the de-assertion of the
DS as the end of the cycle.