Curtiss-Wright SCRAMNet+ SC150 VME6U, Hardware Reference Manual, Page: 57 / 162

OPERATION
Copyright 2007 5-9 VME6U HARDWARE REFERENCE
5.7 Interrupt Controls
SCRAMNet
+
allows a processor to receive interrupts from and/or transmit interrupts to
any other processors on the network, including the originating processor. Table 5-3
indicates the various sources for interrupt control.
5.7.1 Interrupt Options
Table 5-3 Interrupt Controls
Condition Register Description
Host Interrupt Enable CSR0[3] Must be set in order to receive any interrupts from the
network.
Receive Interrupt Enable (RIE) ACR[0] Generates an interrupt to the host from network data
received at the associated shared-memory location.
Transmit Interrupt Enable (TIE) ACR[1] Generates an interrupt message to the network for a
host WRITE to the associated shared-memory
location.
Interrupt on Memory Mask Match
Enable CSR0[5] Permits a shared memory interrupt. Must be set in
order to receive any interrupts from the network.
Override RIE CSR0[6] Generates an interrupt to the host regardless of the
ACR RIE setting upon receipt of any network interrupt
message.
Enable Interrupt on Error CSR0[7] Generates an interrupt request as specified in the
CSR9 Mask register as the corresponding bit in CSR1
is set.
Network Interrupt Enable CSR0[8] Permits transmission of interrupt data to the network.
Override TIE CSR0[ 9] Transmits interrupt message to the network
regardless of the ACR TIE setting.
Reset Interrupt FIFO CSR0[13] Toggle from ‘0’ to ‘1’ to ‘0’ to reset Interrupt FIFO.
Interrupts Armed CSR1[14] During the interrupt operation indicates conditions to
receive interrupt are active. If ‘0’, no interrupts will be
received by the host. Any WRITE to CSR1 will reset
to ‘1’.
Enable Interrupt on Own Slot CSR2[10] In conjunction with CSR2[9] enables host self-
interrupt.
LSP of Interrupt Address CSR4[15:0] Interrupt Address A[15:0].
MSP of Interrupt Address CSR5[6:0] Interrupt Address A[22:16]. Works in conjunction with
CSR4[15:0].
Interrupt FIFO Not Empty CSR5[15] When ‘0’, Interrupt FIFO is empty. If ‘1’, CSR5 and
CSR4 contain legitimate interrupt address.
Receive Interrupt Override CSR8[10] When set, all incoming network messages are treated
as interrupt messages.
Interrupt on Error Mask CSR9[15:0] Interrupts for specific error/status conditions .
VME Interrupt Priority Level (IRQ) CSR15[7:1] 7-bit, host-specific register that holds the VME
Interrupt Levels