Curtiss-Wright SCRAMNet+ SC150 VME6U, Hardware Reference Manual, Page: 47 / 162

INSTALLATION
Copyright 2007 4-15 VME6U HARDWARE REFERENCE
4.8.3 Memory
MEMORY ADDRESSING
The memory base address is software configurable anywhere through the A24 and A32
address space. If the shared-memory and CSR addresses should overlap, the CSR s will
be decoded making the overlapped memory inaccessible.
The Least Significant Word (LSW) of shared-memory address is in CSR10[15:12]. The
Most Significant Word (MSW) of shared-memory address is contained in CSR11[15:0].
SHARED MEMORY
SMA_ENABLE CSR10[0] must be set ON to enable the shared-memory address
decoder.
4.9 Byte Swapping
Some computer systems use different methods of byte ordering. Some have the high bits
arranged from right to left (Little Endian) and other have the high bits going from left to
right (Big Endian). Motorola is an example of a Big-Endian system. Intel is an example
of a Little-Endian system.
Table 4-9 is a simplified summary for 8-bit, 16-bit, and 32-bit byte ordering for big
endian and little endian.
Table 4-9 Big Endian - Little Endian Comparisons
Size Big Endian Little Endian
byte (8-bit) 12 34 56 78 78 56 34 12
shortword (16- bit) 1234 5678 5678 1234
longword (32-bit) 12345678 12345678
The SCRAMNet-LX and SCRAMNet
+
product line has adopted the big-endian ordering
philosophy as the default for data passing. SCRAMNet-LX and SCRAMNet
+
do not
have a built-in byte-ordering conversion function.
4.10 Troubleshooting
On UNIX-like systems, the driver will output a message on boot up similar to the
following:
S installed and on line
If this message does not appear then one or more of the following is not correct:
•
Physical address for the CSRs switch selection on the board.
•
VME address bus for the CSRs (16- or 24-bit)
•
The address for the CSRs in the system files is not correct.
•
The driver was not installed into the new kernel properly.