Curtiss-Wright SCRAMNet+ SC150 VME6U Page 35 Hardware Reference Manual Download

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INSTALLATION

4-3

VME6U HARDWARE REFERENCE

Figure 4-2 VME6U Layout

Summary of Contents for SCRAMNet+ SC150 VME6U

Page 1: ...SC150 VME6U Hardware Reference Document No D T MR VME6U A 0 AA ...

Page 2: ......

Page 3: ...d to the implied warranties of merchantability and fitness for a particular purpose Copyright 2007 Curtiss Wright Controls Inc All Rights Reserved SCRAMNet is a registered trademark of Curtiss Wright Controls Inc U S Patent 4 928 289 UNIX is a registered trademark of UNIX System Laboratories Inc a wholly owned subsidiary of Novell Inc ST is a registered trademark of AT T Revised July 16 2007 Curti...

Page 4: ...n which may interfere with other radio and communication devices The user may be in violation of FCC regulations if this device is used in other than the intended market environments CE As a component part of another system this product has no intrinsic function and is therefore not subject to the European Union CE EMC directive 89 336 EEC ...

Page 5: ... 5 2 6 1 Network Interrupt WRITEs 2 6 2 6 2 Selected Interrupt 2 6 2 6 3 Forced Interrupt 2 8 2 7 External Triggers 2 8 2 8 General Purpose Counter Global Timer 2 8 2 9 LED Status Indicators 2 9 2 10 Modes of Operation 2 9 2 10 1 Data Filter Mode 2 9 2 10 2 High Performance HIPRO Mode 2 10 2 10 3 VME Holdoff Mode 2 10 2 10 4 Loopback Modes 2 11 2 10 5 Write Me Last Mode 2 12 3 PRODUCT OVERVIEW 3 1...

Page 6: ...ion 4 10 4 6 4 Fiber optic Cables 4 10 4 6 5 Fiber optic Connection 4 11 4 7 Install Fiber Optic Bypass Switch Optional 4 12 4 7 1 Auxiliary Connection 4 12 4 8 Internally Configure the Board 4 13 4 8 1 Node Identification 4 14 4 8 2 Network Time out 4 14 4 8 3 Memory 4 15 4 9 Byte Swapping 4 15 4 10 Troubleshooting 4 15 4 10 1 Other H W Considerations 4 16 4 10 2 Customer Support 4 16 5 OPERATION...

Page 7: ...9 5 11 3 Loopback Modes 5 20 5 11 4 Node Insert Mode 5 25 5 11 5 VME Holdoff Mode 5 26 5 11 6 Write Me Last Mode 5 28 5 12 Quad Switch 5 28 APPENDICES APPENDIX A SPECIFICATIONS A 1 APPENDIX B CSR DEFINITIONS B 1 APPENDIX C CSR SUMMARY C 1 APPENDIX D CABINET KIT D 1 APPENDIX E HOST ACCESS TIMING E 1 APPENDIX F CONFIGURATION AIDS F 1 GLOSSARY GLOSSARY 1 INDEX INDEX 1 ...

Page 8: ...re 4 8 Variable Length Messages J4 4 7 Figure 4 9 Ground J6 4 8 Figure 4 10 External Trigger Connections J7 4 8 Figure 4 11 Fiber optic ST Connector 4 10 Figure 4 12 Fiber optic Connections 4 11 Figure 4 13 Inserted State Power On 4 12 Figure 4 14 Bypass State Power Off 4 12 Figure 4 15 Auxiliary Connection 4 13 Figure 5 1 Memory Sharing With Virtual Paging 5 2 Figure 5 2 Transmit Interrupt Logic ...

Page 9: ... Table 4 8 EEPROM Initialization 4 14 Table 4 9 Big Endian Little Endian Comparisons 4 15 Table 5 1 SCRAMNet Message Contents 5 4 Table 5 2 ACR Functions 5 8 Table 5 3 Interrupt Controls 5 9 Table 5 4 Interrupt Error Status Conditions 5 14 Table 5 5 General Purpose Counter Timer Modes 5 16 Table 5 6 Data Filter Options 5 17 Table 5 7 Monitor and Bypass Mode States 5 21 Table 5 8 Wire Loopback Mode...

Page 11: ...r identification followed by the bit or range of bits in brackets For example CSR6 4 CSR3 15 0 ACR 1 2 Bit values are shown in single quotes for example set bit 15 to 1 Code and monitor screen displays of input and output are boxed and indented on a separate line Text that represents user input is bolded Text that the computer displays on the screen is not bolded For example C ls file1 file2 file3...

Page 12: ...st respected standardization authority assessed Curtiss Wright Controls Quality System BSI s Quality Assurance division certified we meet or exceed all applicable international standards and issued Certificate of Registration number FM 31468 on May 16 1995 The scope of Curtiss Wright Controls registration is Design manufacture and service of high technology hardware and software computer communica...

Page 13: ...0 252 5601 E mail DTN_support curtisswright com Fax 937 252 1465 World Wide Web address www cwcembedded com 1 5 Ordering Process To learn more about Curtiss Wright Controls products or to place an order please use the following contact information Hours of operation are from 8 00 a m to 5 00 p m Eastern Standard Daylight Time Phone 937 252 5601 or 800 252 5601 E mail DTN_info curtisswright com Wor...

Page 15: ... the network This is why it is also referred to as replicated shared memory A good analogy is the COMMON AREA used by the FORTRAN programming language Where the COMMON AREA makes variables available to subroutines of a program SCRAMNet makes variables available to processors of a network The SCRAMNet memory size can range from either 4 KB or 128 KB on board memory to 8 MB of expansion memory Avail...

Page 16: ...DE OUT All Reads All Writes P1 ASIC Host Interface Logic Replicated Shared Memory Interrupt FIFO Network Control Logic Transceiver FIFO Receiver Transmitter Transmitt FIFO Dual Port Memory Controller Port 1 Host Port 2 Network Receiver FIFO P2 Figure 2 1 Functional Diagram ...

Page 17: ...hen the Transmit FIFO reaches a FULL condition CSR1 0 ON one more host WRITE could cause a message to be lost To prevent this the CSR controllable built in SCRAMNet feature called VME Holdoff extends the computer WRITE cycle until the Transmit FIFO is able to empty at least one message 2 3 2 Transceiver FIFO This buffer is used to receive foreign messages from the network and send them on or to ho...

Page 18: ...very rapidly When the node operates in BURST or BURST PLUS mode the node will never re transmit its own messages for error correction When operating in PLATINUM or PLATINUM PLUS mode error detection is enabled and re transmission can occur BURST MODE BURST mode is an open loop non error corrected communication mode This mode allows multiple 82 bit messages 46 bit header plus 32 bite data and four ...

Page 19: ...r interrupt action s are to be taken whenever writing to any byte of the SCRAMNet shared memory 4 byte word Only five bits of the ACR are associated with every four byte word of shared memory on even four byte boundaries The other 27 bits of the ACR are phantom bits and do not physically exist 2 6 Interrupts SCRAMNet allows a node processor to receive interrupts from and transmit interrupts to any...

Page 20: ...shared memory locations may also be used to generate signals to external triggers The procedure for selecting shared memory locations for interrupts and or external triggers is explained in the paragraph on the Auxiliary Control RAM paragraph 2 5 OUTGOING INTERRUPT The Outgoing Interrupt is described in Figure 2 3 If both Transmit Interrupt Enable ACR 1 and Network Interrupt Enable CSR0 8 are set ...

Page 21: ...s Address Data Interrupt Bit RING NETWORK LOGIC RING CSR 4 CSR 5 A16 A0 A22 A16 A22 A0 RIE D31 D0 A22 A0 D31 D0 1 Figure 2 4 Incoming Interrupt NETWORK ERRORS The Interrupt on Network Errors mode is enabled by setting CSR0 7 ON Network errors are defined in CSR1 according to an interrupt mask set in CSR9 When an incoming foreign message generates an interrupt there is no way to mask the interrupt ...

Page 22: ...network message interrupt bit does not need to be set 2 7 External Triggers Two external triggers are supported by SCRAMNet VME6U The external triggers will occur only if the ACR has been configured to enable them Triggers 1 and 2 are generated by SCRAMNet shared memory access Both triggers generate a 26 64 ns TTL level compatible non terminated output Trigger 1 Host Read Write ACR 2 enables Trigg...

Page 23: ...by the node FOREIGN MESSAGE The green Foreign Message LED becomes active when the message received is from another node 2 10 Modes of Operation 2 10 1 Data Filter Mode When SCRAMNet Data Filtering is enabled only those WRITEs to SCRAMNet memory that produce a data change are transmitted to the network EXAMPLE If location 1000 in SCRAMNet memory contains the value 20 and the host processor WRITEs t...

Page 24: ...he network The 32 bit WRITE to the network will only occur when all four bytes within the 32 bit location have been written through subsequent WRITEs by the host CPU This can be accomplished by four consecutive 8 bit or two consecutive 16 bit WRITEs to the SCRAMNet memory NOTE HIPRO WRITE will not work if Disable Host to Memory Write CSR2 8 is set or when writing two separate shortwords while usin...

Page 25: ...CARD LOOPBACK MODE Mechanical Switch Media Card Loopback mode is enabled by setting Mechanical Switch Override CSR8 11 to OFF This test is used to check the circuitry up to and including a major portion of the Media Card but excludes the fiber optic circuitry In this test the signal does not leave the Media Card FIBER OPTIC LOOPBACK MODE The Fiber optic Loopback mode must have the optional Fiber O...

Page 26: ...this data is not immediately written to the host node s memory but is first sent to the other nodes on the network When the message returns to the originating node it is written to shared memory and is then removed from the network ring Therefore host originated data written to shared memory travels the ring updating the SCRAMNet node memories on the ring and upon returning to the originating node...

Page 27: ...es A ring topology with 150 Mbit s line transmission rate A Data Filter that allows only data stored in shared memory that has changed to be communicated to the other network nodes Field Upgrade Memory Options up to 8 MB of replicated shared memory for each node processor BURST Mode protocol Error Correction Disabled with fixed length message packets of 82 bits BURST PLUS Mode communication based ...

Page 28: ...g for shared memory CSR selectable Variable length message packet capability Dual port memory Dual vector memory error interrupt single level interrupt Single slot solution EEPROM initialization 3 2 VMEbus Specification Level The SCRAMNet VME6U host board was designed in accordance with the VMEbus specification Revision C 3 ANSI IEEE Std 1014 1987 Slave device SADO32 No UAT no BLT A32 A24 memory A...

Page 29: ...ay be of the READ MODIFY WRITE type Three byte unaligned transfers are not permitted 3 4 2 I O Data transfers to the I O control area of the SCRAMNet VME6U host interface can be 8 16 or 32 bits wide and may be of the READ MODIFY WRITE type Three byte unaligned transfers are not permitted 3 5 Interrupt Capability The SCRAMNet VME6U host interface is an interrupter of the type D08 Interrupt level 1 ...

Page 30: ...some Media Cards This switch allows for fast bypass on power fail conditions The electronic switch operates in the low nanosecond range compared to 20 millisecond for a typical mechanical switch In case of node power failure the electronic switch restores the network so quickly that only one or two messages will have to be retransmitted whereas a mechanical switch could cost an excessive amount of...

Page 31: ... detected If carrier is not detected the port is put into Isolate state and the port is bypassed thereby retaining ring integrity The auxiliary connector and the associated control cable links the port to the node to allow the application running the node to switch the Quad Switch in and out of Include or Isolate state A manual Include Isolate switch is used to guarantee that a node is isolated or...

Page 33: ... switches S1 S7 Set bus resolution switch S8 Set verify Software Compatibility jumper J2 Set verify Memory Configuration jumper J3 Set verify Variable Length jumper J4 Set verify Ground jumper J6 Set verify External Trigger connections J7 Install the board Select cabling options Install Fiber Optic Bypass Switch optional Internal Configuration Set Node Identification CSR3 BITS 15 8 Set Network Tim...

Page 34: ...Network node consists of a single board as shown in Figure 4 2 If the optional memory upgrade was ordered it will come already installed In the event that any shipping damage has occurred notify Curtiss Wright Controls Inc or your supplier immediately 4 3 1 SIMM Connections If SIMMs are installed press gently downward on each SIMM and make sure the clips are engaged to hold the SIMM in place 4 3 2...

Page 36: ...nstalled on J5 the Media Card Signals pass through to P2 row A See Appendix A section A 6 for the pinout description Connection J8 26 1 corresponds to connection P2 26 1 Refer to the SCRAMNet Network Cabinet Kit Hardware Reference for more details 4 4 Externally Configure the Board 4 4 1 EEPROM EEPROM WRITE JUMPER J303 To enable the EEPROM WRITE place a 2 pin header on the top row as viewed from t...

Page 37: ...000000 Table 4 1 Setting the CSR Physical Address Switch Physical Address S1 A31 A30 A29 A28 S2 A27 A26 A25 A24 S3 A23 A22 A21 A20 S4 A19 A18 A17 A16 S5 A15 A14 A13 A12 S6 A11 A10 A09 A08 S7 A07 A06 Not used Not used Table 4 2 Example of a CSR Address S1 S2 S3 S4 A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 1 A B C S5 S6 S7 A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 3 0 0 0 Table 4...

Page 38: ...st be software compatible with SCRAMNet Classic interrupt addressing set place a 2 pin header on the bottom row as viewed from the face plate edge of the board Figure 4 5 Factory default setting OFF Figure 4 5 Software Compatibility J2 4 4 5 Memory Configuration J3 Figure 4 6 Memory Configuration J3 If no SIMMs are installed two options are available 4 KB memory install a 2 pin header on the botto...

Page 39: ... density or high density they can not be mixed To install SIMMs set the SIMM in the slot and gently press back and down until the clips snap into place Figure 4 7 To remove the SIMMs push the clips gently to the outside with each thumb while gently pulling the SIMM toward you with your index fingers 4 4 6 Variable Length Enable VL_EN J4 If the network will be using variable length message packets ...

Page 40: ...nerates two external triggers Activating the triggers for any shared memory location will cause an external trigger to be generated when the shared memory location is accessed Figure 4 10 Table 4 4 and Table 4 5 Figure 4 10 External Trigger Connections J7 Table 4 4 Trigger Pin Connections J7 Pins Output 1 TRIG2 2 TRIG1 3 TRIG1 or TRIG2 4 GROUND Table 4 5 External Trigger Actions Trigger ACR Action...

Page 41: ... power turned ON Watch the Operator s Console for any booting problems that may occur due to improper settings which correspond to illegal address space or improper seating of the node 4 6 Select Cabling Options 4 6 1 Cabinet Kit Connection The SCRAMNet board that is configured to work with the cabinet kit has no Media Card of its own The cabinet kit configuration is discussed in Appendix B FIBER ...

Page 42: ...nated with SMA connectors Maximum node separation using coax is 30 meters The recommended coaxial cable is RG 58 4 6 4 Fiber optic Cables The optional paired fiber optic cables are shipped in a separate carton The fiber optic cables are to be attached to the connectors on the SCRAMNet board or the Cabinet Kit as appropriate Remove the rubber boots on the fiber optic transmitters and receivers as w...

Page 43: ... down stream node Data flows from the transmitter pair of one node to the receiver pair of the next node as described in Figure 4 12 Node 1 Node 2 Node 3 IN OUT IN OUT IN OUT Rx Tx Rx Tx 1 2 1 2 Figure 4 12 Fiber optic Connections NOTE It does not matter if Tx1 or Tx2 is connected to the next node s Rx1 or Rx2 as long as both Tx cables are connected to both of the next node s Rx connectors ...

Page 44: ...gure 4 14 Bypass State Power Off 4 7 1 Auxiliary Connection The optional Fiber Optic Bypass switch is used to provide an uninterrupted fiber optic path when the node is not powered up The Auxiliary Connection at the Media Card is used for communication with the Fiber Optic Bypass Switch The 8 pin modular in line plug male pin connection Figure 4 15 is defined in Table 4 6 The view in Figure 4 15 i...

Page 45: ... a cold boot is determined by the settings of the EEPROM as indicated in Table 4 7 Table 4 7 EEPROM Table 0 2 4 6 8 A C E 00 0000 0000 C040 XX00 XX00 0010 0000 0000 10 0800 0FF0 0000 0000 0000 0000 0000 0020 0000 0000 0000 0000 0000 0000 0000 0000 70 XXXX YYYY YYYY 5555 ZZZZ 5555 5555 5555 NOTE XXXX 00A1 ASIC1 00B1 ASIC2 YYYY ignore ZZZZ Serial Number The board comes with power up default values i...

Page 46: ... the CSRs When the system is powered down and powered up again the CSRs will be reinitialized to these EEPROM values 4 8 1 Node Identification All nodes in the ring must have a unique Node ID To set the Node ID WRITE a unique value 8 bit number between 0 and 255 to CSR3 15 8 4 8 2 Network Time out The recommended value for the Network Time out is NODES IN RING TOTAL LENGTH OF CABLE IN METERS 50 1 ...

Page 47: ... Endian system Intel is an example of a Little Endian system Table 4 9 is a simplified summary for 8 bit 16 bit and 32 bit byte ordering for big endian and little endian Table 4 9 Big Endian Little Endian Comparisons Size Big Endian Little Endian byte 8 bit 12 34 56 78 78 56 34 12 shortword 16 bit 1234 5678 5678 1234 longword 32 bit 12345678 12345678 The SCRAMNet LX and SCRAMNet product line has a...

Page 48: ...orrectly The interrupt request level is set too high 7 The memory is installed at an improper boundary for the size of memory For example a 2 MB board can not be installed at hex address 10500000 However 10400000 or 10600000 are on 2 MB boundaries 4 10 2 Customer Support If the system does not boot correctly reseat the board and double check cable connections If problems persist call Curtiss Wrigh...

Page 49: ...d to handle the interrupts triggered by the SCRAMNet node An example of a generic ISR is included at the end of this section Figure 5 11 page 5 29 5 2 Shared Memory Global variables are mapped directly onto the replicated shared memory The application program typically contains a list of variables or arrays which are stored in a contiguous space and which are to be shared across processors The ana...

Page 50: ...essage with a network address of 6 MB will be written to shared memory at 2 MB Any WRITE accesses to the lower 4 MB will be ignored since there is no memory addressed there To produce a network address the host WRITE adds the relative SCRAMNet address and virtual page offset relative address virtual page offset network address For example 12340 400000 412340 This network address is then transmitte...

Page 51: ...the network 5 2 3 Control Status Registers The SCRAMNet boards are controlled through CSRs for node status setting interrupt vectors setting interrupt locations receiving interrupt addresses mode control and other functions These registers may be accessed by linking to the I O page and reading from or writing to the registers as if they were memory The method used to access the registers depends o...

Page 52: ...rity READ CSR1 to check for any error conditions 5 5 Network Ring Data is passed from one node to the next by fiber optic or coaxial cable Given a three node network configuration with nodes A B and C the following connections would be made The transmitter pair from node A is connected by fiber optic cable to the receiver pair of the next node B The transmitter pair from node B is connected by fib...

Page 53: ...messages onto the network ring This mode uses a 4 byte fixed length message packet for data transfer PLATINUM MODE The PLATINUM mode is BURST mode with error correction enabled PLATINUM mode is enabled by setting CSR2 12 OFF CSR2 14 ON and CSR2 15 OFF See the Protocol Mode Definition table Appendix B page B 8 PLUS MODES The PLUS mode protocol is available as an option to the SCRAMNet BURST and PLA...

Page 54: ...n it increases the node latency The SCRAMNet device automatically increases PLUS mode throughput when blocking is not used when needed due to high throughput host very busy network etc ERROR CORRECTION Error correction is the automatic retransmission of a SCRAMNet Network message when the original message is received in error by the originating node The message will be retransmitted indefinitely u...

Page 55: ...f 6 5 MB sec could be achieved if only one node were transmitting data assuming the host CPU could offer the data at that rate When more than one node is transmitting in BURST mode then the effective output per node is 6 5 MB sec divided by the number of transmitting nodes In BURST and BURST PLUS modes the node never retransmits its own messages In the BURST PLUS mode a 256 byte packet provides 16...

Page 56: ...e ACR Enable bit is zero Table 5 2 ACR Functions Bit Function 0 Receive Interrupt Enable RIE 1 Transmit Interrupt Enable TIE 2 External Trigger 1 3 External Trigger 2 4 HIPRO Location Enable 7 5 Reserved In order for the ACR values to take effect for interrupt action the following SCRAMNet CSR actions should be considered for the type of interrupt operation desired Host Interrupt Enable CSR0 3 to ...

Page 57: ...pt on Error CSR0 7 Generates an interrupt request as specified in the CSR9 Mask register as the corresponding bit in CSR1 is set Network Interrupt Enable CSR0 8 Permits transmission of interrupt data to the network Override TIE CSR0 9 Transmits interrupt message to the network regardless of the ACR TIE setting Reset Interrupt FIFO CSR0 13 Toggle from 0 to 1 to 0 to reset Interrupt FIFO Interrupts ...

Page 58: ... node downstream WRITE a non interrupt value to memory from at least one node This will enable all powered node transmitters and check for fiber optic ring integrity READ CSR1 to check for any error conditions Set CSR6 to the proper interrupt vector number Install the interrupt service routine Set CSR0 to 0x812B to enable receive and transmit interrupts Set CSR0 to 0x81AB to enable Interrupt On Er...

Page 59: ...RENCE ACR TIE HOST WRITE OVERRIDE TIE NETWORK INTERRUPT ENABLE TRANSMIT INTERRUPT SLOT TO NETWORK TRANSMIT NON INTERRUPT SLOT TO NETWORK CSR0 9 CSR0 8 NO NO ACR 1 YES YES YES NO TRANSMIT ENABLE CSR0 1 MUST BE ACTIVE Figure 5 2 Transmit Interrupt Logic ...

Page 60: ... CSR0 or CSR8 MASKED OR SELECTED INTERRUPT The masked or selected interrupt method requires choosing SCRAMNet shared memory locations on each node to receive and or transmit interrupts These shared memory locations may also be used to generate signals to external triggers The procedure for selecting shared memory locations for interrupts and or external triggers is explained in paragraph 5 6 Auxil...

Page 61: ...E INTERRUPT TO HOST NO INTERRUPT TO HOST PLACE ADDRESS INTO INTERRUPT FIFO NO INTERRUPT TO HOST CSR1 NETWORK ERROR MESSAGE PACKET NATIVE MSG ERROR MASK BIT SET CSR9 RECEIVE INT OVERRIDE INTERRUPT MESSAGE NO NO YES YES NO NO YES YES YES NO NO NO YES YES CSR8 10 OVERRIDE RIE ENB INT ON Rx IN OWN SLOT WRITE OWN SLOT ENB NO YES YES NO NO RECEIVE ENABLE CSR0 0 MUST BE ACTIVE YES NO YES Figure 5 3 Recei...

Page 62: ... Memory Mask Match Enable CSR0 5 is set then an interrupt will be generated to the host computer Additional information about each error condition is contained in Appendix B Table B 2 CSR1 If a Network Error is received Figure 5 3 and if Interrupt on Error CSR0 7 and Host Interrupt Enable CSR0 3 are set and Interrupts are Enabled CSR1 14 then the message generates an interrupt to the host If addit...

Page 63: ...et memory address of the data received from the network interrupt Every READ of CSR5 and CSR4 will automatically increment the FIFO pointer to the next interrupt address for both registers CSR4 should be read only if Interrupt FIFO Not Empty CSR5 15 is set Continue to READ CSR5 and CSR4 until the Interrupt FIFO Not Empty bit is zero Writing any value to CSR1 will re enable interrupts See Page 5 29...

Page 64: ...mmed by changing CSR9 13 and CSR9 14 to select the desired mode as described in Table 5 5 CSR8 9 can be set to override the counter timer mode settings and allow the counter timer to run free at 26 66 ns 37 5 MHz CSR9 12 can be set to generate an interrupt upon overflow of the counter timer The output from the event counter timer is stored in CSR13 See Appendix B pages B 6 B 12 and B 14 for more i...

Page 65: ...gister after 100 ms To obtain a starting value of 8717 subtract 56 818 from 65535 The counter timer will not roll over until it reaches 65 535 1 See Appendix B pages B 6 B 12 and B 14 for additional information 5 11 Modes of Operation 5 11 1 Data Filter Many implementations of shared memory tend to rewrite data values to memory that have not actually changed In order to reduce network traffic the ...

Page 66: ...ght 2007 5 18 VME6U HARDWARE REFERENCE DATA FILTER LOGIC DO NOTHING YES SAME WRITE TO MEMORY NEW DATUM OLD DATUM NO READ WRITE HOST CPU NETWORK RING NETWORK RING SHARED MEMORY NETWORK LOGIC Figure 5 4 Data Filter Logic ...

Page 67: ...WRITE is initiated or a total of 4 byte WRITEs if a byte WRITE is initiated to a HIPRO location Otherwise it is possible to partially WRITE a 32 bit location causing the data to be lost and never transmitted The HIPRO mode is also effective for transmitting user defined 16 bit data items Two 16 bit data items may be sent as one 32 bit data item if they are consecutive and lie within the same 32 bi...

Page 68: ... transmit receive circuitry The loopback mode routes data that would normally be transmitted on to the network directly back to the node from different points Table 5 7 depicts the data path for the Monitor and Bypass mode Table 5 8 depicts the data path for Wire Loopback Mode Table 5 9 depicts the data path for Mechanical Switch Loopback Mode Table 5 10 depicts the data path for the Fiber optic L...

Page 69: ...Bypass Mode States State Register Setting Receive Enable CSR0 0 ON Transmit Enable CSR0 1 DON T CARE Insert Enable CSR0 15 OFF Enable Wire Loopback CSR2 7 OFF Media Card Rx Tx Rx Tx Internal PLL and Data Recovery MECHSWITCH ENABLE WIRE LOOPBACK INSERT FO Conv FO Conv Fiber Optic Bypass Switch Optional RX ENABLE TX ENABLE OFF ON OFF ON OFF ON OFF ON Figure 5 5 Monitor and Bypass Mode ...

Page 70: ...gnal does not leave the board Table 5 8 Wire Loopback Mode States State Register Setting Receive Enable CSR0 0 ON Transmit Enable CSR0 1 ON Insert Enable CSR0 15 OFF Enable Wire Loopback CSR2 7 ON Media Card Rx Tx Rx Tx Internal PLL and Data Recovery MECHSWITCH ENABLE WIRE LOOPBACK INSERT FO Conv FO Conv Fiber Optic Bypass Switch Optional RX ENABLE TX ENABLE OFF ON OFF ON OFF ON OFF ON Figure 5 6 ...

Page 71: ...ck Mode States State Register Setting Receive Enable CSR0 0 ON Transmit Enable CSR0 1 ON Insert Enable CSR0 1 5 ON Enable Wire Loopback CSR2 7 OFF Mechanical Switch Override CSR8 11 OFF Media Card Rx Tx Rx Tx Internal PLL and Data Recovery MECHSWITCH ENABLE WIRE LOOPBACK INSERT FO Conv FO Conv Fiber Optic Bypass Switch Optional RX ENABLE TX ENABLE OFF ON OFF ON OFF ON OFF ON Figure 5 7 Mechanical ...

Page 72: ...r optic Loopback Mode States State Register Setting Receive Enable CSR0 0 ON Transmit Enable CSR0 1 ON Insert Enable CSR0 15 ON Enable Wire Loopback CSR2 7 OFF Disable Fiber optic Loopback CSR2 6 OFF Mechanical Switch Override CSR8 11 ON Media Card Rx Tx Rx Tx Internal PLL and Data Recovery MECHSWITCH ENABLE WIRE LOOPBACK INSERT FO Conv FO Conv Fiber Optic Bypass Switch Optional RX ENABLE TX ENABL...

Page 73: ...e the Fiber optic Loopback mode set CSR2 6 ON This state allows data to be transmitted and received on the network ring for this node When the Fiber optic Loopback mode is enabled CSR2 6 OFF the Fiber Optic Bypass Switch does not allow network data to be received by the node Likewise no data can be transmitted by the node into the network ring When power is lost to the Fiber Optic Bypass Switch Fi...

Page 74: ...Holdoff set CSR8 1 OFF The VME Holdoff feature automatically slows down CPU data WRITEs to the SCRAMNet memory when the Transmit FIFO becomes full The Transmit FIFO serves as a buffer between the SCRAMNet memory and the SCRAMNet network The Transmit FIFO can become full when the host CPU is writing to SCRAMNet memory faster than the network can absorb the data If a CPU is capable of writing to the...

Page 76: ...ble Host to Shared Memory Write 5 12 Quad Switch The Quad Switch is a switching center and is used to dynamically configure active SCRAMNet and SCRAMNet ring s The Quad Switch provides dynamic configuration of up to five separate rings Each separate ring is connected to a port on the Quad Switch Refer to Figure 5 10 Each ring can be isolated from the other rings or can be included with one or more...

Page 77: ... will be invoked Interrupts will be disabled until re armed by writing to CSR1 Until that time all other interrupts will be written into the Interrupt FIFO where they can be processed in the Interrupt Service Routine If Interrupts on Errors is enabled then an interrupt due to an error has occurred if the interrupt FIFO is empty on the initial check of CSR5 in the Interrupt Service Routine Read CSR...

Page 79: ...cation A 4 A 5 J8 Connector Pinout A 5 A 6 P2 SCRAMNet Pinout Row A A 6 A 7 P2 SCRAMNet Pinout Row C A 7 A 7 1 Fiber Optic Bypass Switch A 8 FIGURES Figure A 1 VME6U Dimensions A 3 Figure A 2 J8 Connector Pinout A 5 Figure A 3 P2 SCRAMNet Pinout Row A A 6 Figure A 4 P2 SCRAMNet Pinout Row A 7 Figure A 5 Fiber Optic Bypass Switch A 8 Figure A 6 Housing Dimensions A 9 ...

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Page 81: ...Node Separation Coax 30 meters Standard Fiber 300 meters Long Link Fiber 3500 meters Shared Memory ASIC 4 KB On board 128 KB Optional Sizes Low Density SIMMs 512 KB 512 KB 1 MB 2 MB High Density SIMMs 2 MB 2 MB 4 MB and 8 MB Effective Per Node Bandwidth 4 bytes packet 6 5 MB sec 256 bytes packet 16 2 MB sec 1024 bytes packet 16 7 MB sec Node Latency 4 bytes packet 250 ns 800 ns 256 bytes packet 25...

Page 82: ...Hardware AS Top Level Assembly D Standard SCRAMNet 6VME 6U 16 BIT VME XXX Memory bytes 04K 04 K 128 128 K 512 512 K L2M 2 M LOW DENSITY H2M 2 M HIGH DENSITY 04M 4 M 08M 8 M X Transmission Media 0 NO Media Card 1 COAX Media Card 2 STANDARD FO Media Card 3 LONGLINK FO Media Card 4 LASERLINK FO Media Card X Variable Used for product variations and or modifications ...

Page 84: ...VMEbus Voltage Specification Mnemonic Description Allowed Variation Ripple Noise Below 10 MHz 5 V 5 V dc 0 25 V 0 125 V 50 Mv 12 V 12 dc power 0 60 V 0 36 V 50 Mv 12 V 12 dc power 0 60 V 0 36 V 50 Mv 5 V STDBY 5 V dc standby 0 25 V 0 125 V 50 Mv GND Ground Reference Not used by SCRAMNet VME6U ...

Page 85: ...ally going to the Media Card to the J5 connector When the four 9 pin headers are installed on J5 the signals pass out the P2 connector 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 P2A_MECHSW P2A_TX0 P2A_TX0 P2A_TX1 P2A_TX1 P2A_F_RELAY P2A_S_DATA P2A_S_DATA P2A_S_DIR P2A_S_DIR P2A_TRIGGER P2A_TRIGGER P2A_S_CLK P2A_S_CLK P2A_RX1 P2A_RX1 P2A_RX0 P2A_RX0 Figure A 2 J8 Connector...

Page 86: ...ctive only when the J5 jumpers are installed for the P2 Cabinet Kit NOTE Unlabled pins are User Defined P2_E_PRE P2_E_CS P2_E_DIN P2_SP1 P2_E_DOUT P2_SP2 P2_E_CK P2_RX0 P2_RX1 P2_S_CLK P2_TRIGGER P2_S_DATA P2_S_DIR P2_F_RELAY P2_TX1 P2_TX0 P2_MECHSW P2_VDD_A31 CAB_VDD Figure A 3 P2 SCRAMNet Pinout Row A ...

Page 87: ...t Row C NOTE Row B is not shown NOTE Unlabled pins are User Defined P2_GND_C1 P2_GND_C3 P2_GND_C5 P2_SP1 P2_GND_C7 P2_SP2 P2_GND_C9 P2_RX0 P2_RX1 P2_S_CLK P2_TRIGGER P2_S_DATA P2_S_DIR P2_VDD_C23 P2_TX1 P2_TX0 P2_VDD_C29 P2_VDD_C31 CAB_GND CAB_VDD Figure A 4 P2 SCRAMNet Pinout Row ...

Page 91: ...ctor Memory Update B 10 Table B 8 CSR7 Interrupt Vector SCRAMNet Error B 10 Table B 9 CSR8 General SCRAMNet Extended Control Register B 11 Table B 10 CSR9 SCRAMNet Interrupt On Error Mask B 12 Table B 11 CSR10 SCRAMNet Shared Memory Address LSW B 13 Table B 12 CSR11 SCRAMNet Shared Memory Address MSW B 13 Table B 13 CSR12 Virtual Paging Register B 14 Table B 14 CSR13 General Purpose Counter Timer ...

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Page 93: ...er and the function of each bit The name of each bit is indicative of its set state The registers are described using bit 0 as the Least Significant Bit LSB For example Inserting 0xA7C3 in a 16 bit register would set bits 0 1 6 7 8 9 10 13 and 15 ON 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 0 0 1 1 1 1 1 0 0 0 0 1 1 A 7 C 3 ...

Page 94: ...Only or Transmit Receive the Transmit FIFO should be cleared If not all buffered transmit messages will be sent out on the network 10 Transmit Only In this mode any received message bypasses the shared memory and is passed on Any message written by the host to node shared memory is transmitted on the network However any received message is not written to node shared memory Transmissions are subjec...

Page 95: ... shared memory location ACR bit 3 External Trigger 2 Setting this bit generates a trigger signal to an external connector whenever there is a network WRITE to this shared memory location ACR bit 4 HIPRO location enable Setting this bit causes the two 16 bit data or four 8 bit items within the 32 bit address boundary to be transmitted as one 32 bit network message CSR2 13 must also be set for this ...

Page 96: ...eed holding area for data flowing through the network NOTE If the R T FIFO were to be reset during active network transmissions the data in the FIFO at that time would be lost and it would cause errors on the downstream nodes in the network ring 13 Reset Interrupt FIFO This bit must be toggled from 0 to 1 and back to 0 to reset the Interrupt FIFO 14 Reset Transmit FIFO This bit must be toggled fro...

Page 97: ... fiber or coax resulting from noise on the transmission lines or a result of hardware failure It can be any one of the following Missing transition for two clock periods on line Parity error or a Framing error 6 Carrier Detect Latched This bit is set if the receivers do not detect any or enough output from the previous nodes transmitters This is usually an indication that the fiber optic lines hav...

Page 98: ...network events free run 26 66 ns and free run 1 706 ns with trigger 2 CLEAR 13 Current Link Latched This bit tells which of the optional redundant transceivers is currently selected as the active link The default value is 1 A 14 Interrupts Armed During interrupt operation this bit indicates that the conditions to receive an interrupt are active If this bit is 0 then the host will receive no interr...

Page 99: ...this bit is purely diagnostic This mode is valid only when the Insert Node CSR0 15 is OFF 8 Disable Host to Memory Write When this bit is set the host WRITEs are not written to the host node s shared memory but are sent out on the network if Transmit CSR0 1 is ON 9 Write Own Slot Enable When this bit is set the originating node can receive the message slot or packet sent out to the network This is...

Page 100: ... to the network Exceptions HIPRO will not work when Disable Host to Memory WRITE CSR2 8 is set HIPRO will not work when writing two separate shortwords while using interrupts 14 Multiple Messages This bit allows multiple native messages on the network It is used in conjunction with CSR2 11 CSR2 12 and CSR2 15 to enable the BURST mode communication protocol see below 15 No Network Error Correction ...

Page 101: ... LSP READ ONLY 15 0 LSP of the Interrupt Address These bits represent the LSP of the interrupt address A15 A0 Bits 0 and 1 are always 0 since the addresses are on four byte boundaries Table B 6 CSR5 Bits Interrupt Address and Status READ ONLY 6 0 MSP of the Interrupt Address These seven bits represent the MSP of the interrupt address A22 A16 When coupled with CSR4 this address represents the SCRAM...

Page 102: ...r must be pre loaded with the vector before interrupt processing can occur 15 8 Reserved Table B 8 CSR7 Bits Interrupt Vector SCRAMNet Error READ WRITE 7 0 Interrupt Vector This host specific register stores the VMEbus interrupt vector for the interrupt generated by a SCRAMNet Error This register must be pre loaded with the vector before interrupt processing can occur 15 8 Reserved Both Interrupt ...

Page 103: ... run at a rate of 37 5 MHz 26 66 ns This counter mode overrides all other counter mode settings 10 Receive Interrupt Override When this bit is set all incoming network messages are treated as interrupt messages 11 Mechanical Switch Override Normally set to ON When OFF Mechanical Switch Loopback Mode is invoked 14 12 Memory Size Configuration These bits indicate the memory size code and are used in...

Page 104: ...tect Fail Mask 7 Bad Message Mask 8 Receiver Overflow Mask 9 Transmitter Retry Mask 10 Transmitter Retry Due to Time Out Mask 11 Redundant TX RX Fault Mask 12 Interrupt on General Purpose Counter Timer Overflow Mask 13 See Below 14 See Below 15 Fiber Optic Bypass Switch Not Connected Mask General Purpose Counter Timer Modes CSR8 9 CSR9 14 CSR9 13 Counter Timer Modes 0 0 0 Count Errors 0 0 1 Count ...

Page 105: ...he on ASIC comparator for shared memory access 11 1 0 Always zero 12 SMA12 13 SMA13 Shared Memory Address 14 SMA14 15 SMA15 Table B 12 CSR11 Bits SCRAMNet Replicated Shared Memory Address MSW 0 SMA16 1 SMA17 2 SMA18 3 SMA19 4 SMA20 5 SMA21 6 SMA22 7 SMA23 This is the most significant part of the replicated shared memory 8 SMA24 9 SMA25 10 SMA26 11 SMA27 12 SMA28 13 SMA29 14 SMA30 15 SMA31 ...

Page 106: ...al Paging Enable When ON this bit enables Virtual Paging 4 1 0 Always zero 5 VP_A12 6 VP_A13 7 VP_A14 8 VP_A15 9 VP_A16 Virtual Page number The significance of this register is dependent on the 10 VP_A17 memory size e g For 4 MB only VP_A22 is valid for 4 KB VP_A 22 12 11 VP_A18 are valid 12 VP_A19 13 VP_A20 14 VP_A21 15 VP_A22 ...

Page 107: ...UNT 2 3 RD_COUNT 3 4 RD_COUNT 4 5 RD_COUNT 5 6 RD_COUNT 6 This is a General Purpose Counter Timer register It can be used to 7 RD_COUNT 7 count trigger 1 and 2 events count errors or other events as 8 RD_COUNT 8 programmed by CSR9 bits 13 and 14 9 RD_COUNT 9 10 RD_COUNT 10 11 RD_COUNT 11 12 RD_COUNT 12 13 RD_COUNT 13 14 RD_COUNT 14 15 RD_COUNT 15 ...

Page 108: ... VME Interrupt Priority Level IRQ Bits reflect the Interrupt Priority Level For example IPL 5 translates to setting bit 5 20 hex Selector Chart Level Bit Hex 7 6 5 4 3 2 1 1 0 0 0 0 0 0 1 0x2 2 0 0 0 0 0 1 0 0x4 3 0 0 0 0 1 0 0 0x8 4 0 0 0 1 0 0 0 0x10 5 0 0 1 0 0 0 0 0x20 6 0 1 0 0 0 0 0 0x40 7 1 0 0 0 0 0 0 0x80 Only one level is set at a time Multiple level selection disables the WRITE operatio...

Page 109: ...ormance HIPRO READ Control Bits Register Only bits 1 and 0 are valid Bit 1 Bit 0 0 1 HIPRO READ enabled 1 1 HIPRO READ ACR enabled Bit 0 is CSR enabled HIPRO READ enabled for every longword address location This is an override bit Bit 1 is ACR selectable HIPRO READ enabled for all ACR HIPRO WRITE ACR 4 locations only Both bits 0 and 1 must also be enabled for this mode 15 2 Reserved ...

Page 111: ...y Update R W C 6 C 8 CSR7 Interrupt Vector SCRAMNet Error R W C 6 C 9 CSR8 General SCRAMNet Extended Control Register C 7 C 10 CSR9 SCRAMNet Interrupt On Error Mask C 8 C 11 CSR10 SCRAMNet Shared Memory Address LSW C 9 C 12 CSR11 SCRAMNet Shared Memory Address MSW C 9 C 13 CSR12 Virtual Paging Register C 10 C 14 CSR13 General Purpose Counter Timer C 10 C 15 CSR14 Reserved C 11 C 16 CSR15 VME Inter...

Page 112: ......

Page 113: ...3 Host Interrupt Enable HIE 4 Auxiliary Control RAM Enable ACRE 5 Interrupt on Memory Mask Match Enable IMME 6 Override RIE Flag ORF 7 Interrupt on Errors IOE 8 Network Interrupt Enable NIE 9 Override TIE Flag OTF 10 Enable Tx Data Filter DFEN 11 Enable Lower 4 Kbytes for Data Filter EN4K 12 RESET Rx Tx FIFO RTRF 13 RESET Interrupt FIFO RSTIF 14 RESET Transmit FIFO RTXF 15 Insert Node INSRT ...

Page 114: ...F 3 Always 0 Not Used 4 Interrupt FIFO Full IFF 5 Protocol Violation PV 6 Carrier Detect Failure CDF 7 Bad Message BB 8 Receiver Overflow RXO 9 Transmit Retry TXRTY 10 Transmit Retry Time out TO 11 Redundant TxRx Fault RTF 12 General Purpose Counter Timer Overflow GPCTO 13 Redundant TxRx Link 1 A 0 B RTLAB 14 Interrupts Armed Write to re arm IARM 15 Fiber Optic Bypass Not Connected FOB ...

Page 115: ...Variable length messages on network VAR_LEN 13 HIPRO Write Enable HIPRO 14 Allow multiple native messages on network MULTIPLE_MSG 15 No Network Error Correction NO_ERR_CRCT Write Me Last Self Interrupt Mode Definition Bit 10 Bit 9 Bit 8 Mode 0 1 1 WRITE ME LAST mode 1 1 0 SELF INTERRUPT mode 1 1 1 WRITE ME LAST with SELF INTERRUPT mode SCRAMNet Protocol Mode Definition CSR2 15 CSR2 14 CSR2 12 CSR2...

Page 116: ... Bit Function Name 0 NN0 1 NN1 2 NN2 3 Node Number Count NN3 4 Valid After a Transmission from the Node NN4 5 NN5 6 NN6 7 NN7 8 NID0 9 NID1 10 NID2 11 Node ID Number NID3 12 NID4 13 NID5 14 NID6 15 NID7 When ID_MUX bit CSR8 0 is set Bits 7 0 are Transmit Age Bits 15 8 are Receive ID ...

Page 117: ...6U HARDWARE REFERENCE C 5 CSR4 Interrupt Address LSP Bit Function Name 0 Always 0 1 Always 0 2 RFA2 3 RFA3 4 RFA4 5 RFA5 6 Interrupt FIFO Address Field LSP RFA6 7 RFA7 8 RFA8 9 RFA9 10 RFA10 11 RFA11 12 RFA12 13 RFA13 14 RFA14 15 RFA15 ...

Page 118: ...g the Transmit Time out value to CSR5 stores it in shadow memory Do not set this value to 0 A value of 0 prevents host generated data from leaving the Transmit FIFO C 7 CSR6 Interrupt Vector Memory Update R W An 8 bit register that holds the VMEbus interrupt vector generated by a memory update Only bits 7 0 are valid 15 8 are reserved C 8 CSR7 Interrupt Vector SCRAMNet Error R W An 8 bit register ...

Page 119: ...RE port CSR_CK 7 DIN line connected to the MICROWIRE DOUT pins E_DIN 8 Initiate initiation sequence CSR Reset CSR_RST 9 Override Counter mode GPC_FRE 10 Receive Interrupt Override RX_INT_OVR 11 1 Mechanical Switch Override C_MECHSW 0 Invoke Mechanical Switch Loopback Mode 12 Memory Size Configuration See below MCI0 13 Memory Size Configuration See below MCI1 14 Memory Size Configuration See below ...

Page 120: ...sk M_BM 8 Receiver Overflow mask M_RX_OVR 9 Transmitter Retry mask M_RETRY 10 Transmitter Retry Time out M_RETRY_T_O 11 Redundant Transmit Receive Fault mask M_FAULT 12 Interrupt on General Purpose Counter Timer Overflow M_COUNT_OVR 13 General Purpose Counter Modes See below M_INC_TRIGS 14 General Purpose Counter Modes See below M_INC_ERRS 15 Fiber Optic Bypass Not Connected mask M_FO_BYPASS Gener...

Page 121: ...parator for SM access SMA_ENABLE 11 1 Reserved 0 12 SMA12 13 Shared Memory Address LSW SMA13 14 SMA14 15 SMA15 C 12 CSR11 SCRAMNet Shared Memory Address MSW Bit Function Name 0 SMA16 1 SMA17 2 SMA18 3 SMA19 4 SMA20 5 SMA21 6 SMA22 7 SMA23 8 SMA24 9 SMA25 10 SMA26 11 SMA27 12 SMA28 13 SMA29 14 SMA30 15 SMA31 Shared Memory Address MSW ...

Page 122: ...B pages B 6 B 12 and B 15 Bit Function Name 0 Counter Timer register RD_COUNT 0 1 Counter Timer register RD_COUNT 1 2 Counter Timer register RD_COUNT 2 3 Counter Timer register RD_COUNT 3 4 Counter Timer register RD_COUNT 4 5 Counter Timer register RD_COUNT 5 6 Counter Timer register RD_COUNT 6 7 Counter Timer register RD_COUNT 7 8 Counter Timer register RD_COUNT 8 9 Counter Timer register RD_COUN...

Page 123: ...ster Only bits 1 and 0 are valid Bit 1 Bit 0 0 1 HIPRO READ enabled 1 1 HIPRO READ ACR enabled Bit 0 is CSR enabled HIPRO READ enabled for every longword address location This is an override bit Bit 1 is ACR selectable HIPRO READ enabled for all ACR HIPRO WRITE ACR 4 locations only Both bits 0 and 1 must also be enabled for this mode 15 2 Reserved C 18 Auxiliary Control RAM R W Bit Function Name 0...

Page 125: ...ptions D 1 D 2 Compact Cabinet Kit D 1 D 3 Expanded Cabinet Kit D 2 D 4 Direct attached P2 Cabinet Kit D 3 FIGURES Figure D 1 Compact Cabinet Kit Connection D 1 Figure D 2 Expanded Cabinet Kit Connection D 2 Figure D 3 Direct attach P2 Cabinet Kit Installation D 3 ...

Page 126: ......

Page 127: ...node s connections and maintains the shielding of the chassis LED indicators at the bulkhead plate remotely indicate the node s status The host interface board configured to work with the cabinet kit has no media card with transmitters or receivers Instead a 20 pin connector and cables form an extension to the cabinet kit and the media card is mounted on the cabinet kit board The Compact model as ...

Page 128: ...s with a faceplate The Expanded cabinet kit has a VME P2 cabling option This permits connection to the cabinet kit board via the P2 backplane connection HOST INTERFACE BOARD HOST ADAPTER BOARD CABLES EXPANDED CABINET KIT BOARD OPTIONAL REDUNDANT MEDIA ACCESS CARD Figure D 2 Expanded Cabinet Kit Connection Additional details concerning features and installation are included in SCRAMNet Network Cabi...

Page 129: ...here is a single connector on the board for a fiber optic or coax media card or a host adapter board Figure D 3 Direct attach P2 Cabinet Kit Installation NOTE The connector can go on two ways When installed properly the notch will be on the P2 row side of the connector Correct installation will result in both the VME6U board and cabinet kit component sides facing the same direction Improper orient...

Page 131: ...nce E 7 E 5 2 Worst Case Condition E 7 E 5 3 Back to Back Host READs E 9 E 5 4 Back to Back Host WRITEs E 11 FIGURES Figure E 1 ASIC Resources E 2 Figure E 2 READ From Internal CSR E 3 Figure E 3 WRITE to Internal CSR E 4 Figure E 4 Non ASIC Resources E 5 Figure E 5 READ From External CSR E 6 Figure E 6 Two Host WRITEs in Contention With Three Network WRITEs E 7 Figure E 7 Back to Back Host READs ...

Page 132: ......

Page 133: ...the host CPU The second port is WRITE ONLY and is connected to the high speed serial network There are three types of accesses to the DPRC They are shown in Table E 1 Table E 1 Dual Port RAM Controller Access Types Access Type Port Cycle Time Host WRITE 1 240 ns Host READ 1 133 ns Network WRITE 2 133 ns E 2 1 Contention The SCRAMNet Network being an intelligent peripheral does buffered WRITEs to s...

Page 134: ...f cycle stretching will rarely if ever occur E 3 Host Interface Logic to Shared Memory CSR The second module is the actual host interface logic needed to interface the ASIC resources memory and internal CSR to the host CPU bus This is the logic that translates all VME host transactions to SCRAMNet This host logic is responsible for determining the format of the access B U S HOST LOGIC N E T W O R ...

Page 135: ...REQ Host Request requested for a particular CSR address Wait for HACK Host Acknowledge to provide READ data Assert DTACK Data Transfer Acknowledge Requester Master CPU de asserts AS and DS end of cycle Figure E 2 is an example of a READ from an internal CSR DTACK AS DSx HREQ HACK 1 5 3 4 2 1 AS to DSx 10 ns per VME Spec 2 DSx to HREQ 80 ns Host Adapter time 3 HREQ 53 ns Host Adapter time 4 End of ...

Page 136: ...ss Data accepted and ASIC asserts HACK Assert DTACK Data Transfer Acknowledge Requester Master CPU de asserts AS and DS end of cycle Figure E 3 is an example of a WRITE to an internal CSR DTACK AS DSx HREQ HACK 1 3 2 1 AS to DSx 10 ns per VME Spec 2 DSx to HREQ 106 ns Host Adapter time 3 HREQ to DTACK 53 ns Host Interface 4 DTACK to End of Cycle 0 ns per VME spec 169 ns Figure E 3 WRITE to Interna...

Page 137: ...CES HOST SPECIFIC RESOURCES Figure E 4 Non ASIC Resources The third module is the actual host logic needed to interface the non ASIC resources external host specific CSR to the host CPU as depicted in Figure E 4 The Interrupt Vector register is a non ASIC resource Timings to this register vary significantly from that of ASIC related resources ...

Page 138: ... DSx to DTACK 186 ns Host Adapter time 3 DTACK to End of Cycle 0 ns per VME Spec 196 ns NOTE There is no Host Request HREQ because this is not an ASIC resource Figure E 5 READ From External CSR E 5 Access Times Host access to shared memory is affected by two things Priority on contention between the two ports Asynchronous request handling There are minimum and maximum times that depend on Network ...

Page 139: ...RC buffer data and address DPRC assert HREQ_PEND HACK asserted Release bus DTACK De assert HREQ_PEND Requester Host CPU de assert DSx and AS End of Cycle DPRC WRITE to shared memory HACK E 5 2 Worst Case Condition The scenario described in all these cases considers the worst case operating condition This is a very unlikely condition and would not occur in an average configuration The maximum timin...

Page 140: ...ations will toggle between network WRITE operations This pattern will repeat itself if the worst case scenario continues every fifth host READ i e HR1 NW1 NW2 HR2 NW3 HR3 NW4 NW5 HR4 Back to Back Host WRITEs In this case the worst case timing would be where three Network WRITE operations will stretch the second host WRITE operation The third and fourth host WRITE are also held off by two Network W...

Page 141: ... End HACK 133 ns DPRC 5 HACK to DTACK 22 ns Host Interface 6 DTACK to End of Cycle 0 ns per VME Spec 271 ns 7 Min AS inactive 30 ns per VME Spec Cycle 2 8 AS to DSx 10 ns per VME Spec 9 DSx to HREQ 80 ns Host Adapter time 10 HREQ to End HACK 257 ns DPRC 11 HACK to DTACK 22 ns Host Interface 12 DTACK to End of Cycle 0 ns per VME Spec 399 ns Figure E 7 Back to Back Host READs Figure E 8 illustrates ...

Page 142: ...work WRITEs DPRC performs READ for host 5 HACK is issued to host interface logic 6 DTACK is asserted bus released 7 DTACK is de asserted AS DSx de asserted End of Cycle SECOND CYCLE 8 AS DSx fall Start of Cycle 80 ns delay to decode address 9 HREQ asserted READ request to DPRC 10 Host interface logic sleeps until HACK is received from DPRC Maximum READ Time DPRC is processing two Network WRITEs 11...

Page 143: ...8 Cycle 1 1 AS to DSx 10 ns per VME Spec 2 DSx to HREQ 106 ns Host Adapter time 3 HREQ to DTACK 53 ns Host Adapter time 4 DTACK to End of Cycle 0 ns per VME Spec 169 ns 5 MIn AS Inactive 30 ns per VME Spec Cycle 2 6 AS to DSx 10 ns per VME Spec 7 DSx to HREQ 586 ns Host Adapter and DPRC time 8 HREQ to DTACK 53 ns Host Adapter time 9 DTACK to End of Cycle 0 ns per VME Spec 649 ns Figure E 9 Back to...

Page 144: ...owledgment DPRC has not yet written to shared memory 6 AS DSx fall Start of second host cycle 7 HREQ cannot be asserted since the previous request is still pending DPRC receives 3 network WRITEs DPRC processes network WRITEs DPRC performs host WRITE to shared memory 8 HREQ_PEND de asserted No longer busy DPRC asserts HREQ_PEND WRITE request accepted DPRC buffers data DPRC asserts HACK Host Interfa...

Page 145: ...F F CONFIGURATION AIDS APPENDIX F CONFIGURATION AIDS ...

Page 146: ......

Page 147: ... intrpt vector data intrpt vector reserved reserved reserved reserved reserved reserved reserved reserved ACR LED STATUS 0 1 2 3 RIE TIE EXT TRG 1 EXT TRG 2 4 5 6 7 HIPRO ENB reserved reserved reserved G G G Y INSERT MESSAGE WAITING CARRIER DETECT ERROR G G NATIVE MESSAGE FOREIGN MESSAGE CSR 1 READ RESET CSR 3 CSR 5 CSR 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TX FIFO FULL TX FIFO NOT EMPTY TX FIFO...

Page 148: ... reserved reserved reserved reserved reserved reserved CSR 9 CSR 11 CSR 13 CSR 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TX FIFO FULL MASK TX FIFO NOT EMP MASK TX FIFO 7 8 FULL MASK BIST STREAM R O RX FIFO FULL MASK PROTOCOL VIOL MASK CARRIER DETECT FAIL MASK BAD MESSAGE MASK RX OVERFLOW MASK TX RETRY MASK TX RETRY TIME OUT REDUN TXRX FAULT MASK GP CTR TIMER OVRFLO UTIL CTR MODES UTIL CTR MODES FO ...

Page 149: ...SCRAMNet NETWORK CONFIGURATION DATA SHEET NODE ID HOST MACHINE MEMORY ADDRESS BUS MEMORY SIZE CSR ADDRESS BUS INT LEVEL SCRAMNet SERIAL ...

Page 150: ......

Page 151: ...1 GLOSSARY GLOSSARY ...

Page 152: ......

Page 153: ...CRAMNet hardware board A pcb its collection of electronic components and either one or two 96 pin connectors that can be plugged into the backplane connectors burst A protocol where messages are transmitted without error correction to gain higher throughput burst Also burst plus A variable packet size enhancement for the burst protocol Maximum packet size may be set to either 256 bytes or 1024 byt...

Page 154: ...t of the interrupt address LSW Lease Significant Word master A functional module that initiates DTB cycles to transfer data between itself and a slave module message packet See packet MSB Most Significant Byte MSP Most Significant Part of the interrupt address MSW Most Significant Word native message A message that is received by the node of origin node latency The time delay at a node before a fo...

Page 155: ...end a message around the network is not received by the originating node within the time out period specified in CSR5 The message will be retransmitted indefinitely by the originating node until it is received correctly by the originating node Valid only in error correction mode PLATINUM ring time The time it takes a message to traverse the network ring from the originating node and back again The...

Page 156: ... sends or receives data in an unaligned fashion VME address space The VME address space varies according to specific VME device and is identified as A16 A24 or A32 space A32 is the largest address space it allows up to 4 gigabytes of space using 32 bit addresses A24 space uses 24 bit addresses and A16 space uses 16 bit addresses VMEbus A standard bus by which small computers and intelligent periph...

Page 157: ...1 INDEX INDEX ...

Page 158: ......

Page 159: ... dual port memory controller 2 1 buffered transmit messages B 2 dual port memory 3 2 built in self test B 12 C 8 F 2 dual port RAM controller E 1 E 6 E 7 E 8 E 9 E 10 E 11 E 12 BURST mode 2 4 3 1 4 14 5 4 5 5 5 6 5 7 5 10 B 8 dual vector memory 3 2 BURST PLUS mode 2 4 3 1 4 13 5 7 B 8 C 3 bus E VMEbus 3 1 3 2 3 3 5 26 A 1 A 4 B 10 C 6 EEPROM bus resolution switch 4 1 initialization program 4 13 C ...

Page 160: ...1 B 2 B 3 B 10 B 16 C 11 F 2 framing error B 5 interrupt request level B 10 G interrupt results 5 8 interrupt service routine 2 5 2 8 5 1 5 14 5 15 5 29 general purpose counter timer 2 8 3 2 5 14 5 16 5 17 B 1 B 6 B 11 B 12 B 15 C 2 C 7 C 8 interrupt servicing 5 3 H interrupt signal 5 10 interrupt vector 2 5 5 10 5 14 B 1 B 10 C 6 E 5 handshaking logic 2 1 interrupt vectors 5 3 high speed transfer...

Page 161: ...3 1 3 2 4 2 memory usage 5 3 PLATINUM PLUS mode 2 4 B 8 message format 5 4 PLUS mode 2 4 5 5 5 6 message length A 1 B 7 PLUS mode protocol 2 4 5 5 message packet 2 4 5 4 B 5 power message packets 2 4 3 5 battery 4 4 message slot 2 4 host 4 4 microwire C 7 F 2 power options 4 4 mode control 5 3 power up B 4 mode operation 5 3 5 6 program size 5 3 monitor and bypass mode 5 20 propagation delay 5 6 m...

Page 162: ... 17 time out 4 13 4 14 5 6 5 7 B 5 timer global mode 2 8 high resolution mode 2 8 sub frame 2 8 transaction host E 2 network E 11 E 12 transmit FIFO B 4 transmit FIFO B 5 transmit enable C 1 transmit FIFO 5 28 transmit FIFO B 2 transmit FIFO C 6 Transmit FIFO B 9 B 12 C 2 transmit FIFO 5 26 transmit interrupt event 5 6 transmit interrupts 2 5 2 6 2 8 5 9 5 10 5 12 transmit retry 5 14 B 5 C 2 trans...

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