Curtiss-Wright SCRAMNet+ SC150 VME6U, Hardware Reference Manual, Page: 143 / 162

HOST ACCESS TIMING
Copyright 2007 E-11 VME6U HARDWARE REFERENCE
E.5.4 Back-to-Back Host WRITEs
Figure E-9 shows access timing for two back-to-back VME WRITEs as fast as possible
according to the VME specification revision C1. The first cycle shows the normal
buffered WRITE cycle and the second cycle shows a stretched WRITE cycle (maximum
hold). As in the VME READ, the host interface logic waits for the first DS to fall and
then delays 106 ns to allow address decode and attain bus stability.
In the first VME cycle, the host logic raises a host WRITE request to the DPRC. The
DPRC accepts the request, buffers the data, and issues a HACK to the Host Interface
logic. The host interface logic responds by asserting DTACK 53 ns later. Under normal
conditions this saves CPU cycles. By VME specification, as soon as the VME bus master
detects DTACK on the bus, the AS and DSx may then be re-asserted to end the cycle.
DTACK*
AS*
DSx*
HREQ
HACK
5
6 1
7
2
3
4
8
Cycle #1
1. AS to DSx = 10 ns (per VME Spec.)
2. DSx to HREQ = 106 ns (Host Adapter time)
3. HREQ to DTACK = 53 ns (Host Adapter time)
4. DTACK to End of Cycle = 0 ns (per VME Spec.) 169 ns
5. MIn. AS Inactive = 30 ns (per VME Spec.)
Cycle #2
6. AS to DSx = 10 ns (per VME Spec.)
7. DSx to HREQ = 586 ns (Host Adapter and DPRC time)
8. HREQ to DTACK = 53 ns (Host Adapter time)
9. DTACK to End of Cycle = 0 ns (per VME Spec.) 649 ns
Figure E-9 Back-to-Back Host WRITEs
FIRST CYCLE
1. AS, DSx fall - Start of Cycle (106 ns delay to decode address).
2. HREQ asserted - WRITE request to DPRC
- DPRC asserts HREQ_PEND Request accepted
- DPRC buffers data
- DPRC asserts HACK.
3. Host interface logic generates DTACK 53 ns later.
4. AS and DSx are de-asserted.
5. Minimum time AS is inactive is 30 ns.
SECOND CYCLE
The second cycle shows a second host WRITE is initiated 30 ns later according to
minimum VME requirements. Under normal operating conditions it is unlikely the host
will be able to turn around that quickly. An HREQ cannot be generated since the first one
is still being serviced. Additionally, in this “worst case” scenario, three network
transactions must be processed before the previous host request is cleared.