Curtiss-Wright SCRAMNet+ SC150 VME6U, Hardware Reference Manual, Page: 139 / 162

HOST ACCESS TIMING
Copyright 2007 E-7 VME6U HARDWARE REFERENCE
E.5.1 Typical Access Sequence
The following is the typical Host READ and Host WRITE sequence with no contention.
READ
AS and DS fall (Start of cycle)
HREQ asserted
HREQ_PEND (Host Request Pending) asserted (DPRC accepts request)
DPRC READ shared memory and pass the data to Host-Interface Logic
De-assert HREQ_PEND
HACK
Release bus (DTACK)
Requester/Host CPU de-assert DSx and AS (End of Cycle)
WRITE
AS and DS fall (Start of cycle)
HREQ asserted
DPRC buffer data and address
DPRC assert HREQ_PEND
HACK asserted
Release bus (DTACK)
De-assert HREQ_PEND
Requester/Host CPU de-assert DSx and AS (End of Cycle)
DPRC WRITE to shared memory
HACK
E.5.2 Worst-Case Condition
The scenario described in all these cases considers the “worst case” operating condition.
This is a very unlikely condition, and would not occur in an average configuration. The
maximum timing values were generated in a laboratory with a “worst case” scenario
emulation. Figure E-6 is a functional diagram of the “worst case” scenario.
B
U
S
HOST
LOGIC
N
E
T
W
O
R
K
HW
NW
DTACK
HACK
ASIC
NW NW
DUAL PORT RAM CONTROLLER
MEMORY
H/W
Figure E-6 Two Host WRITEs in Contention With Three Network WRITEs