Curtiss-Wright SCRAMNet+ SC150 VME6U, Hardware Reference Manual, Page: 118 / 162

CSR SUMMARY
Copyright 2007 C-6 VME6U HARDWARE REFERENCE
C.6 CSR5 - Interrupt Address (MSP) and Status (READ Only*)
Bit Function Name
0 RFA16
1 RFA17
2 RFA18
3 Interrupt FIFO Address Field (MSP) RFA19
4 RFA20
5 RFA21
6 RFA22
13-7 Reserved 0
14 Retry Bit in Interrupt FIFO (RF_RETRY)
15 Interrupt FIFO Not Empty (~RX_F_E)
*
Writing the Transmit Time-out value to CSR5 stores it in shadow memory. Do not set
this value to ‘0’. A value of ‘0’ prevents host-generated data from leaving the Transmit
FIFO
C.7 CSR6 - Interrupt Vector (Memory Update) (R/W)
An 8-bit register that holds the VMEbus interrupt vector generated by a memory update.
Only bits [7:0] are valid; [15:8] are reserved.
C.8 CSR7 - Interrupt Vector (SCRAMNet
+
Error) (R/W)
An 8-bit register that holds the VMEbus interrupt vector generated due to a SCRAMNet
+
error. Only bits [7:0] are valid; [15:8] are reserved.