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Summary of Contents for BIART

Page 1: ...r Cromemco BIART Communication Processor Instruction Manual _ November 1984 CROMEMCO Inc P O Box 7400 280 Bernardo Avenue Mountain View CA 94039 023 20H Rev A Copyright 1984 CROMEMCO Inc All Rights R...

Page 2: ...co SpellMaster Program and formatted by the Cromemco Word Processing System Formatter II Camera ready copy was printed on a Cromemco 3355B printer The following are registered trademarks of Cromemco I...

Page 3: ...l BIART Interrupts Host Interrupts BIART Host Communications Host Commands to the BIART BIART Status to the Host Host Data to the BIART BIART Data to the Host LIST OF APPENDICES Appendix A BIART Regis...

Page 4: ...IARTRS 232C Interface 4 8 8 9 Figure B 1 RS 232C Interface Wiring Figure B 2 RS 422 Interface Wiring Figure B 3 RS 423 Interface Wiring 38 38 39 LIST OF TABLES 1 1 Host BIARTCommunication Ports 6 1 2...

Page 5: ...RxC CTS RTS OCD and DTR Asynchronous 30 5 to 19 200 baud with x16 clock multiplier baud rate varied by dividing a local crystal controlled 5 5 MHz clock by a programmable 16 bit scale factor synchron...

Page 6: ...erface S 100 IEEE 696 Power Operating Environment Two bi directional S 100 IEEE 696 bus I O ports S 100 IEEE 696 maskable vectored interrupts 8 VOC 1 5 A 18 VOC 250 mA 18 VOC 250 mA o 55 degrees Celsi...

Page 7: ...clude a ROMbootstrap program which loads an application program and then switches to 64 Kbytes of RAM for maximum buffer space The two serial channel scan 0 perate independently of one another in asy...

Page 8: ...renUl1W uont T1J SUI JoSsat OJd UOnl1t UnWW0 J LlIVHI ot wawoJ J...

Page 9: ...p B if the ROMhas an access time of 150 n8ec or less and setting switch 8W 1 to select an 8 100 base port address After the board is set up insert it in an empty 8 100 bus slot with power off Connect...

Page 10: ...J2 Interrupt Priority J1 Serial Channel A J3 Serial Channel B B Cut Jumper For 150 nsec ROM Reset J4 Parallel Figure 1 1 THE BIART BOARD...

Page 11: ...nds If you want to use a faster ROM 150 nSec or less cut jumper B between IC19 and IC20 see figure 1 1 BIART BASE I O ADDRESS The host processor and the BIART communicate through two bi directional S...

Page 12: ...gure 1 1 The Reset connector resets the BIART board J2 connects the BIART in the S 100 interrupt priority chain J1 connects to serial channel A J3 connects to serial channel B and J 4 connects to a Ce...

Page 13: ...B BIT 0 OUT TxD A2 TxD B2 GROUND TxC A TxC B SENSE RxD A RxD B BIT 7 IN RxC A RxC B BIT 5 IN RxC A RxC B BIT 3 IN RTS A2 RTS B2 BIT 1 IN DTR A DTR B NMI WAIT BIT 7 OUT DTR A2 DTR B2 BIT 5 OUT DTR A2 D...

Page 14: ...hird connector to the next highest and so on The suggested order of board priorities is 64FOC 16FOC STOC OCTART TU ART lOP BlART MAXIMIZER GPIB CTI PRI and SCC The order of the boards between the 64FO...

Page 15: ...s attached to the system housing rear panel installed above align the red cable stripe of each cable with the BIART board legend arrowheads and attach the 26 pin female connectors to BIART connectors...

Page 16: ...01 pmuuV j uon n qsuI Jossa OJd Uo w unwwoo J lIVIH o llIawoJO...

Page 17: ...ion and decry ption managing the parallel printer monitoring data integrity and attempting all possible error recovery procedures for the host processor The BIART program store is 16 Kbytes of ROM fro...

Page 18: ...roup the command and status registers each access multiple Z SCC registers Through register Channel B Command for example the BIART Z80B can write to 16 channel B internal registers WRO through WRl5 S...

Page 19: ...move the reset condition 4 A software reset If BIART switch SW 1 section 8 is ON see figure 1 1 then the host can reset the BlART board by sending the following six bytes to register Commands From Hos...

Page 20: ...supply a variable interrupt vector which pinpoints the channel and interrupt condition within the channel when the BlART Z80B acknowledges the request These conditions include Tx Buffer Empty Rx Chara...

Page 21: ...askable interrupt request The BIART does this by setting bit Enable Host Interrupts in register BIART Control and then writing an interrupt vector to register Interrupt Vector To Host When the vector...

Page 22: ...t read the previous status word and the BIART should hold off writing a new one otherwise the previous status word will be overwritten There is no fixed status bit available to alert the host that a n...

Page 23: ...ata To Host Empty is reset the host has not read the previous data byte and the BlART should hold off writing a new one otherwise the previous data byte will be overwritten The host determines that a...

Page 24: ...81 1 mu ew uont nJ suI Jossat OJd uOJwt Junwwo J HVIH ot wawoJ...

Page 25: ...the BIART Host software The command sequence 7Eh 55h OFh 70h 2Ah 7Eh is reserved for software reset see the section BIART RESET in chapter 2 for details These bits are not affected by a BIART reset a...

Page 26: ...hardware controlled data output by the BIART to this bit position is ignored This bit is reset immediately after the host processor writes a data byte to register Data From Host This bit is set signif...

Page 27: ...is reset as the host processor writes a byte to register Command From Host The BIART must set this bit for the host under program control since the bit is not automatically set when the BIART reads re...

Page 28: ...first time Bit Data From Host Available of register BIART Flags is set to alert the BIART that a data byte from the host is available in this register When the BIART reads register Data From Host bit...

Page 29: ...he BIART is available in this register When the host reads register Data To Host bit Data To Host Empty of register BIART Flags is set to alert the BIART that it may output a new data byte If the BIAR...

Page 30: ...eads the Data To Host register This event may optionally be programmed to generate an internal BIART interrupt by setting bit Enable BIART Interrupts of register BIART Control A BIART reset forces thi...

Page 31: ...BIART outputs a byte to register Status To Host A BIART reset forces this bit to 1 DO Command From Host Available This bit is set as the host processor writes a byte to register Command From Host Thi...

Page 32: ...es either a Z80B interrupt mode IM1 or 1M2response is automatically placed on the internal BIART data bus during Interrupt Acknowledge Resetting this bit inhibits this feature This bit is automaticall...

Page 33: ...Enable Host Interrupts is reset then BIART outputs to this register are null operations If there is more than one S IOO interrupt source BIART interrupt requests are prioritized by the S IOO interrup...

Page 34: ...Bit 5 In Connector J4 Bit 4 In Connector J4 Bit 3 In Connector J4 Bit 2 In Connector J4 Bit 1 In Connector J4 Bit 0 In Connector J4 LSB This register reads 8 parallel input bits from BIART connector...

Page 35: ...3 Out Connector J4 Bit 2 Out Connector J4 Bit 1 Out Connector J4 Bit 0 Out Connector J4 LSB This register writes 8 parallel output bits to BIART connector J4 in non inverted form see table 2 1 The dig...

Page 36: ...e most significant hex digit must be a 4 while the least significant hex digit may be any value Oh through Fh DO RAM ROM A BIART reset forces this bit set If this bit is set BIART on board memory is c...

Page 37: ...Bit 0 in RR12 is the LSB of the current 16 bit Channel B time constant See Reference 2 for descriptions of all read register bits Only RROcan be read directly from BIART register Channel B Status wit...

Page 38: ...multiplier character length parity and so on before the channel is used See Reference 2 for descriptions of all write register bits Only WROcan be directly accessed through BIART register Channel B Co...

Page 39: ...haracters are queued for reading The top of the FIFO feeds register Channel B Receive Data When an assembled character rises to the top of the FIFO bit Rx Character Available in register RRO is set th...

Page 40: ...into the Channel B transmitter either immediately or as soon as the preceding character is completely shifted out Bit Tx Buffer Empty of register RROis set whenever the buffer becomes empty and is res...

Page 41: ...ister Channel B Status Register CHANNEL A COMMANDS BIART Host OUT 52h No Access See the description of register Channel B Commands Register CHANNEL A RECEIVE DATA BIART Host IN 53h No Access See the d...

Page 42: ...9f lImuuw uon nJ SuI JOSS900Jd uonu UnWwo8 J HVIa O W9UIOJ8...

Page 43: ...nded Differential 50 FT 2000 FT 4000 FT20K 300K 101 1 2V Difference 5V to l5V 3 6V to 5 4V Driver output resis Ro 300 ohms 100uA between 100uA between 6 to 6V 6 and 25V circuit current lSC 500mA l50mA...

Page 44: ...TXD A I Pin 3 RXD I I I MC3488 I I I 5v I I I I AM26LS32 I I RXD A I Pin 2 TXD I I I N C RXD A I I I I I I I Figure B 1 RS 232C INTERFACE WIRING BIART I CABLE DCE I I I TXD A2 I Pin 14 I I I R I TXD...

Page 45: ...Interfaces In figure B 2 resistor R is a termination resistor and the Enable bit is bit 3 of the BIART control register refer to appendix A TXD A RXD A BIART TXD A Pin 3 GND Pin 7 5v AM26lS32 RXD A P...

Page 46: ...Ov Tanuaw uont T1J SUI JossaOOJd uonat Junruruo L HVIH ot ruaruoJ...

Page 47: ...SIX BIT TRANSCODE OOh SOH 20h A 21h B 22h S C 23h T D 24h U E 25h V F 26h W G 27h X H 28h Y I 29h Z STX 2Ah ESC 2Bh 2Ch BEL 2Dh ENQ SUB 2Eh ETX ETB 2Fh HT 30h 0 J 31h 1 K 32h 2 L 33h 3 M 34h 4 N 35h 5...

Page 48: ...pmU B1AI uono T1J SUI Jossao OJd UOn BO unwwoo L HVm oO wawoJO...

Page 49: ...Ah J 6Ah jVT CONTROL K 2Bh 4Bh K 6Bh k FF CONTROL L 2Ch 4Ch L 6Ch 1 CR CONTROL M 2Dh 4Dh M 6Dh m SO CONTROL N 2Eh 4Eh N 6Eh n SI CONTROL O 2Fh 4Fh 0 6Fh 0 DLE CONTROL P 30h 0 50h P 70h P DC1 CONTROL Q...

Page 50: ...renuew UOn t1 I SUI JossaOOJdUo w unwwoJ J HVIH o waWOJJ...

Page 51: ...g D6h 0 VT 3Dh NAK 88h h D7h P FF 3Fh SUB 89h i D8h Q CR 40h SPACE 91h j D9h R SO 4Ah c 92h k EOh SI 4Bh 93h 1 E2h S DLE 4Ch 94h ID E3h T OC1 4Dh 95h n E4h U OC2 4Eh 96h 0 E5h V OC3 4Fh I 97h P E6h W...

Page 52: ...9f7 pmu BW UOHOT1J suIJossat OJd uOJwo unwwo J HVIS oowawo I...

Page 53: ...Support 011 0095 017 0006 27128 ROM 502 0096 017 0071 74ALS157 010 0412 74LS244 010 0100 74LS373 010 0102 MC3488 010 0416 74ALS175 010 0358 74LS32 010 0058 Z8530A 011 0109 017 0006 74LS08 010 0064 74...

Page 54: ...0 0100 74LS174 010 0097 4164 150nS RAM 011 0079 7805 340T 5 012 0001 7912 012 0014 7407 010 0104 AMZ8121 010 0328 82S159 502 0072 017 0004 74LS373 010 0102 74LS244 010 0100 4164 150nS RAM 011 0079 Dio...

Page 55: ...0061 Capacitor NetworKs Designation Cromemco Part No 2 47 pf 8 pin 005 0000 Resistors Designation Cromemco Part No 1 Kohm1 4 watt 001 0018 47 ohm 1 4 watt 001 0003 470 ohm 1 4 watt 001 0014 22 ohm 1...

Page 56: ...10 pin 003 0014 75 ohm 4R 8 pin 003 0080 1 Kohm 7R 8 pin 003 0007 100 ohm 5R 10 pin 003 0093 4 7 Kohm 7R 8 pin 003 0009 100 ohm 7R 8 pin 003 0036 4 7 Kohm 9R 10 pin 003 0014 330 ohm 4R 8 pin 003 0004...

Page 57: ...a s _ Q _ o tj 8 I 00 00 o 1 4 00 2 Q _ o s It s It L j r t TT C bD REV 1 l I I D 11 BUS i I I I I j I1 1 l l a G Q GJG G5G 1 Il j 15 1 718 I 1 N r D J 11 Q1 i OR 01 D IS DJ Dl IZ 8 D D 3 1fr irT n _j...

Page 58: ...i r 1 u rutin nll MINAI At1Y W 8 30 L 7 t 1 _ 2 3 O IA j1 AL A t SEL1 LT61 no i 1 t j lkl lo rrI T ll NALTIt IN6 1 q L 1 1 K I J3 10 Eil12 I fn l rF ntJc Ol lLY i l I JOT c1N __ J m_ _ t 1JrI r 7 3 11...

Page 59: ...2 Q o 11 I 11 L R AD 1 j 1 l cc I l liT El AR F snR 3Crom meo l tRN 3 1K 1 l e1 Q _ _ 13 _ Vt 4 I l It D 8 _ I _ 1 1 vffi J 7 M _ L 2 u W 74LSD4 r 141 40 21 t ___ _ lI Ji f il n I 1 wl JZ V 30 13 4D 4...

Page 60: ...Sjlj 15 05 D 60 j 3 50 SG 12 __ Db R I I 1 3D 30 D Jli o Dj D7 11 I r r A t 2 3 I DI 100 If 5 I 1 kA 2 r3 L_ I 2AZ 72 0 7 2 0 4 71 S tA4 I 4 f 4 5 H b IA3 IY3 4 rll2 IYl 1 0 d IAI YI X jF 3S Jj t1 j D...

Page 61: ...33 Channel B status register 31 Channel B transmit data register 34 Command from host available bit 15 25 Command from host empty bit 15 21 Commands from host register 15 19 Configure memory register...

Page 62: ...host register 15 27 Interrupt vector FAh FCh 14 26 Interrupts host 15 Interrupts internal BIART 14 Interrupts parallel port 14 Interrupts Z SCC 14 Jumper ROM speed 5 Memory configuration BIART 5 13 30...

Page 63: ...set S 100 bus 13 Reset software BIART 13 Reset Z80B 13 ROM BIART memory 5 RRO RR13 registers Z SCC 31 RS 232C levels BIART 9 Set up BIART 3 Set definition 1 Six bit transcode 41 Status 5 4 3 2 bit 20...

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Page 65: ...ESS OR IMPLIED ANY IMPLIED WARRANTIES INCLUDING IMPLIED WARRANTIES OF MERCHANTABILlTY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXCLUDED WHERE SUCH EXCLUSION IS ALLOWED AND OTHERWISE LIMITED IN DURATIO...

Page 66: ......

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