4. Functions
CNT32-4MT(LPCI)
55
Control of a sampling
The CNT32-4MT(LPCI) can use a sampling clock to collect sampling data at fixed time intervals. The
sampling clocks, sampling start triggers, and sampling stop triggers are listed below.
Table 4.5. Sampling clock / start / stop
Item Factor
Description
Note
Not used
Sampling is not used.
Set for counter mode.
Internal clock
Internal clock(50nsec to 107sec) 25nsec unit
Sampling clock
External clock
Fall of external sampling clock input (EXTCLK)
(Maximum frequency response of 10 MHz)
Not used
Sampling is not used.
Set for counter mode.
Software
Software command
Rise of an external
signal
Rise of external sampling start signal
(EXTSTART)
Fall of an external
signal
Fall of external sampling start signal
(EXTSTART)
Sampling start
trigger
Count match
When the count value for channel 0 to 3 matches
the value in comparison register 0 or 1
Not used
Sampling is not used.
Set for counter mode.
Software
Software command
Rise of an external
signal
Rise of external sampling stop signal
(EXTSTOP)
Fall of an external
signal
Fall of external sampling stop signal
(EXTSTOP)
Count match
When the count value for channel 0 to 3 matches
the value in comparison register 0 or 1
Specified number of
times
Terminated after sampling for the specified
number of times
Sampling stop
trigger
Bus master error
When FIFO memory has become full
-
Sampling can be controlled by one clock, start, and stop trigger per board. One sampling start trigger
per board and one sampling stop trigger per board are available. Triggering on the rising or falling
edge can be selected.
-
The first sampling data is collected when a sampling start trigger is input (not synchronized with the
sampling clock). Collection of the second and subsequent sampling data is synchronized with the
sampling clock. Note that this means that the time between the first and second samples may be less
than the specified sampling clock period.
-
Sampling halts immediately when the sampling stop trigger is input. No sampling data is collected at
or after the time when sampling stops.
-
Although the sampling clock can be set as fast as 50nsec, this is for sampling of one channel only. If
the number of sampled channels is greater, the minimum sampling clock period becomes the
number of sampling channels x 50nsec.
Example: Minimum sampling clock for 4-channel sampling = 4 x 50 nsec = 200 nsec
