3. Setup
28
CNT24-2(USB)GY
Digital Filter
According to the using environment, the Chattering Noise and Cross Talk may be
presented in phase-A, B or Z of the counter.
It would result in counting error. Use digital filter to avoid this abnormity.
Digital filter clock setting data determines the sampling clock cycle for the digital
filter. When detecting 4 clocks of continuous HIGH (or LOW) signals by sampling the
input signals with this sampling clock, the digital filter outputs a HIGH (or a LOW),
and transmits the signal to the counter circuit. In other words, the signals that is
shorter than the sampling clock × 4, they can be cancelled from the counter data.
Notice that because all external input signals (with the exception of general-purpose
input signals) are directed into the internal counter through the digital filter, they are
read with a delay of 4 sampling clock cycles.
In the initial condition, external input signals are read with a delay of 0.4
µ
sec.
Figure 3.13.
Digital Filter
Points
- In the initial condition, the clock is set at 0.1
µ
sec (which is the default).
- Some noise signals can cause a delay greater than 4 clock cycles.
- Any change in level occurring at a frequency faster than a set sampling clock cycle is
invalidated and the level is not correctly counted. Therefore, signals less than the
input frequency must be entered.
Same as 4 pulses
* Same as the LOW level
External input pin
Count input
Sampling clock
Cancel
Count data
0
1
Summary of Contents for CNT24-2GY
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