7. About Hardware
68
AIO-160802GY-USB, AI-1608GY-USB
Control Signal Timings
Control Signal Timings for Analog Input
Figures 7.4, 7.5, 7.6, and Table 7.3 show the control signal timings for the analog input function.
Figure 7.4. Timing Chart of External Sampling Clock
Figure 7.5. Timing Chart of Sampling Start Control Signal
Figure 7.6. Timing Chart of Sampling Stop Control Signal
Table 7.3. Control Signal Timings
Parameter
Symbol Time
Unit
Delay from external sampling clock cycle to first channel hold
t
DEH
250
nsec
Delay from external sampling clock cycle to first channel A/D conversion start
pulse
t
DEC
250
nsec
Set up time of sampling start (Rising edge)
t
SRS
100
nsec
Hold time of sampling start (Rising edge)
t
HRS
100
nsec
Set up time of sampling start (Falling edge)
t
SFS
100
nsec
Hold time of sampling start (Falling edge)
t
HFS
100
nsec
Set up time of sampling stop (Rising edge)
t
SR P
100
nsec
Hold time of sampling stop (Rising edge)
t
HRP
100
nsec
Set up time of sampling stop (Falling edge)
t
SFP
100
nsec
Hold time of sampling stop (Falling edge)
t
HFP
100
nsec
The times listed in Table 7.3 are for standard operating conditions.
t
DEC
External Smapling Clock Input
t
DEH
Conversion start
Sample / Hold
External Smapling Start Trigger Input
t
HRS
t
SRS
t
HFS
t
SFS
External Smapling Stop Trigger Input
t
HRP
t
SRP
t
HFP
t
SFP
CAUTION
