
6. Appendix
PT-955LXC-DC5311 User’s manual
93
SERIAL I/O Address and Register Function
The following table lists the I/O addresses in case of SERIAL A.
Table 6.4. I/O Address
I/O address DLAB Read/Write
Register
W
Transmitter holding register
THR
0
R
Receive buffer register
RBR
03F8H
1
W
Divisor latch register (LSB)
DLL
1
W
Divisor latch register (MSB)
DLM
03F9H
0
W
Interrupt enable register
IER
03FAH
X
R
Interrupt ID register
IIR
03FBH
X
W
Line control register
LCR
03FCH
X
W
Modem control register
MCR
03FDH
X
R
Line status register
LSR
03FEH
X
R
Modem status register
MSR
03FFH X R/W
Scratch
register
SCR
DLAB (Divisor Latch Access Bit) : The value in bit 7 of the line control register.