Congatec COM Express conga-TC87 User Manual Download | Manualshive

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Copyright

©

2013

congatec

AG

TU87m12

90/114

Feature

Options

Description

Limit CPUID Maximum

Disabled

Enabled

When enabled, the processor limits the maximum CPUID input value to 03h when queried, even if the processor
supports a higher CPUID input value.
When disabled, the processor returns the actual maximum CPUID input value of the processor when queried.
Limiting the CPUID input value may be required for older operating systems that cannot handle the extra CPUID
information returned when using the full CPUID input value.

Execute Disable Bit

Disabled

Enabled

Enable or disable the Execute Disable Bit (XD) of the processor. With the XD bit set to enabled, certain classes of

malicious buffer overflow attacks can be prevented when combined with a supporting OS.

Intel Virtualization Technology

Disabled

Enabled

When enabled, a VMM can utilize the integrated hardware virtualization support.

Hardware Prefetcher

Disabled

Enabled

Enable or disable the Mid Level Cache (L2) streamer prefetcher.

Adjacent Cache Line Prefetch

Disabled

Enabled

Enable or disable the Mid Level Cache (L2) prefetching of adjacent cache lines.

CPU AES

Disabled

Enabled

Enable or disable CPU Advanced Encryption Standard (AES) instructions.

EIST

Disabled

Enabled

Enable or disable Enhanced Intel SpeedStep Technology (EIST).

Energy Performance

Performance

Balanced
Perform.
Balanced Energy

Energy Efficient

Optimize between performance and power savings.

Turbo Mode

Disabled

Enabled

Enable or disable Turbo Mode.

Package Power Limit Lock

Disabled

Enabled

When enabled, PACKAGE_POWER_LIMIT MSR will be locked and a reset will be required to unlock the register.

CPU Power Limit1

0-255
Default : 0

CPU Power Limit1 value

CPU Power Limit1 Time

0-255
Default : 0

Time window in which the Power Limit1 is maintained.

CPU Power Limit2

0-255
Default : 0

CPU Power Limit2 value

Platform Power Limit Lock

Disabled

Enabled

When enabled, PLATFORM_POWER_LIMIT MSR will be locked and a reset will be required to unlock the register.

CPU Power Limit3

0-255
Default : 0

CPU Power Limit3 value

CPU Power Limit3 Time

0-255
Default : 0

Time window in which the Power Limit3 is maintained.

CPU Power Limit3 Duty Cycle

0-100
Default : 0

Specify in percentage the duty cycle that the CPU is required to maintain over the configured Power Limit3 time

windows.

DDR Power Limit1

0-255
Default : 0

DDR Power Limit1 value

DDR Power Limit1 Time

0-255
Default : 0

Time window in which the DDR Power Limit1 is maintained.

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Summary of Contents for COM Express conga-TC87

Page 1: ...Copyright 2013 congatec AG TU87m12 1 114 COM Express conga TC87 4th Generation Intel Core i7 i5 i3 and Mobile Intel Celeron Single Chip Ultra Low TDP Processors User s Guide Revision 1 2 ...

Page 2: ...on 10 BIOS Setup Description 1 2 2014 10 24 AEM Added three additional variants to conga TC87 Options Information table in section 1 and updated section 2 5 Power Consumption Added note about the high CMOS current drawn by rev C x and earlier in section 2 6 1 CMOS Battery Power Consumption Added note about the ULP mode in section 6 1 4 Gigabit Ethernet Updated section 6 2 3 Digital Display Interfa...

Page 3: ...or indirectly from any technical or typographical errors or omissions contained herein or for discrepancies between the product and the user s guide In no event shall congatec AG be liable for any incidental consequential special or exemplary damages whether based on tort contract or otherwise arising out of or in connection with this user s guide or any other information contained herein or the u...

Page 4: ...on that should be observed Terminology Term Description GB Gigabyte 1 073 741 824 bytes GHz Gigahertz one billion hertz kB Kilobyte 1024 bytes MB Megabyte 1 048 576 bytes Mbit Megabit 1 048 576 bits kHz Kilohertz one thousand hertz MHz Megahertz one million hertz TDP Thermal Design Power PCIe PCI Express SATA Serial ATA PEG PCI Express Graphics PCH Platform Controller Hub eDP Embedded DisplayPort ...

Page 5: ...pon specifications will be repaired or exchanged at congatec s option and expense Customer will obtain a Return Material Authorization RMA number from congatec AG prior to returning the non conforming product freight prepaid congatec AG will pay for transporting the repaired or exchanged product to the customer Repaired replaced or exchanged product will be warranted for the repair warranty period...

Page 6: ...hnical support for our customers so that our products can be easily used and implemented We request that you first visit our website at www congatec com for the latest documentation utilities and drivers which have been made available to assist you If you still require assistance after visiting our website then contact our technical support department by email at support congatec com C ERTIFICATIO...

Page 7: ...ows A B C D 26 6 1 Primary Connector Rows A and B 27 6 1 1 Serial ATA SATA 27 6 1 2 USB 2 0 27 6 1 3 High Definition Audio HDA Interface 27 6 1 4 Gigabit Ethernet 27 6 1 5 LPC Bus 28 6 1 6 I C Bus Fast Mode 28 6 1 7 PCI Express 28 6 1 8 ExpressCard 29 6 1 9 Graphics Output VGA CRT 29 6 1 10 LCD LVDS eDP 29 6 1 11 General Purpose Serial Interface 29 6 1 12 Power Control 30 6 1 13 Power Management 3...

Page 8: ...Monitoring Submenu 82 11 4 5 PCI PCI Express Submenu 83 11 4 5 1 PCI Express Settings Submenu 84 11 4 5 2 PIRQ Routing IRQ Reservation Submenu 85 11 4 5 3 PCI Express Port Submenu 85 11 4 6 ACPI Submenu 87 11 4 7 RTC Wake Submenu 88 11 4 8 Trusted Computing Submenu 88 11 4 9 CPU Submenu 89 11 4 10 SATA Submenu 93 11 4 10 1 Software Feature Mask Configuration Submenu 94 11 4 11 Intel R Rapid Start ...

Page 9: ...lash Interface Signal Descriptions 54 Table 15 Miscellaneous Signal Descriptions 55 Table 16 General Purpose I O Signal Descriptions 55 Table 17 Power and System Management Signal Descriptions 56 Table 18 General Purpose Serial Interface Signal Descriptions 57 Table 19 Power and GND Signal Descriptions 57 Table 20 Connector A B Pinout 58 Table 21 PCI Express Signal Descriptions general purpose 60 ...

Page 10: ...stable data throughput The COM computer on module integrates all the core components and is mounted onto an application specific carrier board COM modules are legacy free design no Super I O PS 2 keyboard and mouse and provide most of the functional requirements for any application These functions include but are not limited to a rich complement of contemporary high bandwidth serial interfaces suc...

Page 11: ...cy 3 3 GHz 2 9 GHz N A N A Memory DDR3L 1600 MT s dual channel 1600 MT s dual channel 1600 MT s dual channel 1600 MT s dual channel Processor Graphics Intel HD graphics 5000 GT3 Intel HD graphics 4400 GT2 Intel HD graphics 4400 GT2 Intel HD graphics GT2 Graphics Max Dynamic Freq 1 1 GHz 1 1 GHz 1 0 GHz 1 0 GHz VGA No No No No LVDS Yes Yes Yes Yes DisplayPort DP Yes Yes Yes Yes HDMI Yes Yes Yes Yes...

Page 12: ...grated flat panel interface with 25 112MHz single dual channel LVDS Transmitter Supports Single channel LVDS interface 1 x 18 bpp or 1 x 24 bpp Dual channel LVDS interface 2 x 18 bpp or 2 x 24 bpp panel VESA LVDS and OpenLDI color mappings Automatic Panel Detection via Embedded Panel Interface based on VESA EDID 1 3 Resolution up to 1920x1200 in dual LVDS bus mode Optional eDP interface NOTE Eithe...

Page 13: ...87 supports the following operating systems Microsoft Windows 8 Microsoft Windows 7 Microsoft Windows Embedded Standard Linux 2 3 Mechanical Dimensions 95 0 mm x 95 0 mm 3 74 x 3 74 Height approximately 18 or 21mm including heatspreader depending on the carrier board connector that is used If the 5mm height carrier board connector is used then approximate overall height is 18mm If the 8mm height c...

Page 14: ...s Input Range Volts Derated Input Volts Max Input Ripple 10Hz to 20MHz mV Max Module Input Power w derated input Watts Assumed Conversion Efficiency Max Load Power Watts VCC_12V 12 12 11 4 12 6 11 4 100 137 85 116 VCC_5V SBY 2 5 4 75 5 25 4 75 50 9 VCC_RTC 0 5 3 2 0 3 3 20 2 4 2 Rise Time The input voltages shall rise from 10 of nominal to 90 of nominal at a minimum slope of 250V s The smooth turn...

Page 15: ...indows 7 Professional 64Bit Hyper Threading enabled Speed Step enabled CPU Turbo Mode enabled and Power Plan set to Power Saver This setting ensures that Core processors run in LFM lowest frequency mode with minimal core voltage during desktop idle Each module was tested while using two 2GB memory modules Using different sizes of RAM as well as one or two memory modules will cause slight variances...

Page 16: ... 12 0 W 12V 100 Workload turbo mode enabled 2 30 A 27 6 W 12V 100 CPU and GPU workload turbo mode disabled 1 59 A 19 1 W 12V 100 CPU and GPU workload turbo mode enabled 2 41 A 28 9 W 12V Peak Power Consumption 2 14 A 28 9 W 12V 2 5 2 Intel Core i5 4300U 1 9 GHz Dual Core 3MB Cache conga TC87 Art No 046902 GT2 Graphics Intel Core i5 4300U 1 9 GHz 2 Core 3MB Intel Smart Cache 22nm Layout Rev TU87LB1...

Page 17: ...N A 100 CPU and GPU workload turbo mode disabled 1 52 A 18 2 W 12V 100 CPU and GPU workload turbo mode enabled N A Peak Power Consumption 1 67 A 20 0 W 12V 2 5 4 Intel Celeron 2980U 1 6 GHz Dual Core 2MB Cache conga TC87 Art No 046904 GT2 Graphics Intel Celeron 2980U 1 6 GHz 2 Core 2MB Intel Smart Cache 22nm Layout Rev TU87LB1 BIOS Rev TU87R005 Max Turbo Frequency N A Memory Size 2 x 2GB Operating...

Page 18: ...100 CPU and GPU workload turbo mode disabled TBD 100 CPU and GPU workload turbo mode enabled N A Peak Power Consumption TBD 2 5 6 Intel Core i3 4010U 1 7 GHz Dual Core 3MB Cache VGA conga TC87 Art No 046903 GT2 Graphics Intel Core i3 4010U 1 7 GHz 2 Core 3MB Intel Smart Cache 22nm Layout Rev TU87LB1 BIOS Rev TU87R005 Max Turbo Frequency N A Memory Size 2 x 2GB Operating System Windows 7 64 bit Pow...

Page 19: ... 3V DC 9 µA The CMOS battery power consumption value listed above should not be used to calculate CMOS battery lifetime You should measure the CMOS battery power consumption in your customer specific application in worst case conditions for example during high temperature and high battery voltage The self discharge of the battery must also be considered when determining CMOS battery lifetime For m...

Page 20: ...ngly recommends that you use the appropriate congatec module heatspreader as a thermal interface between the module and your application specific cooling solution If for some reason it is not possible to use the appropriate congatec module heatspreader then it is the responsibility of the operator to ensure that all components found on the module operate within the component manufacturer s specifi...

Page 21: ...nect PCIe0 PCIe1 PCIe2 PCIe3 PCIe5 L0 PCIe5 L1 PCIe5 L2 eDP to LVDS Bridge HUB congatec System Management Controller X X X X X X PCIe5 L3 X X X X X X 2x SO DIMM X1 X2 SPI Flash 0 SPI Flash 1 LVDS eDP VGA supported only on rev C x and later Ethernet 10 100 1000 Intel I218LM Optional DP to VGA Only on rev C x and later TPM XDP LPC I2C SATA0 SATA3 USB 2 0 SM Bus UART0 1 Ethernet CRT LVDS eDP COM Expr...

Page 22: ...e that the heatspreader is attached directly to the systems chassis thereby using the whole chassis as a heat dissipater For additional information about the conga TC87 heatspreader refer to section 4 1 of this document Caution There are mounting holes on the heatspreader designed to attach the heatspreader to the module These mounting holes must be used to ensure that all components that are requ...

Page 23: ...heatspreader screws is 0 3 Nm Mechanical system assembly mounting shall follow the valid DIN IS0 specifications Caution When using the heatspreader in a high shock and or vibration environment congatec recommends the use of a thread locking fluid on the heatspreader screws to ensure the above mentioned torque specification is maintained ...

Page 24: ...perature Board Temperature Sensor The CPU temperature sensor T00 is located in the CPU U1 This sensor measures the CPU temperature and is defined in CGOS API as CGOS_TEMP_CPU The board temperature sensor T01 is located in the congatec Board Controller cBC This sensor measures the board temperature and is defined in CGOS API as CGOS_TEMP_BOARD The sensor locations are shown below CPU Sensor Locatio...

Page 25: ...de of the module This sensor measures the temperature of the DRAM module and is defined in CGOS API as CGOS_TEMP_BOTDIMM_ENV The DRAM sensor location is shown below Note The DRAM sensor is not populated on conga TC87 standard variants The sensor is only available as a build time option Optional DRAM sensor location Build Time Option ...

Page 26: ...ts of rows C and D In this view the connectors are seen through the module top view C D A B A B 4 PCI Express Lanes 4x Serial ATA 8x USB 2 0 High Definition Audio I F Gigabit Ethernet connected via a x1 PCI Express Lane LPC Bus 2x Serial Interface UART I C Bus Fast Mode LVDS eDP SM Bus SPI GPIOs Power Control Power Management Fan Control C D 2x USB 3 0 2x HDMI Routed to DDI interface at connector ...

Page 27: ...e A B connector The EHCI host controller in the PCH supports these interfaces with high speed full speed and low speed USB signalling The controller complies with USB standard 1 1 and 2 0 For more information about how the USB host controllers are routed see section 8 5 6 1 3 High Definition Audio HDA Interface The conga TC87 provides an interface that supports the connection of HDA audio codecs 6...

Page 28: ...s yet with a significantly reduced number of signals Due to the software compatibility to the ISA bus I O extensions such as additional serial ports can be easily implemented on an application specific baseboard using this bus See section 10 1 1 for more information about the LPC Bus 6 1 6 I C Bus Fast Mode The I C bus is implemented through the congatec board controller Texas Instruments Tiva TM4...

Page 29: ...d stream in LVDS format The bridge supports single and dual channel signalling with color depths of 18 bits or 24 bits per pixel and pixel clock frequency up to 112 MHz Note The LVDS eDP interface supports either LVDS or eDP signals Both signals are not supported simultaneously 6 1 11 General Purpose Serial Interface Two TTL compatible two wire ports are available on Type 6 COM Express modules The...

Page 30: ...r board hardware must drive this signal low until all power rails and clocks are stable Releasing PWR_OK too early or not driving it low at all can cause numerous boot up problems It is a good design practice to delay the PWR_OK signal a little typically 100ms after all carrier board power rails are up to ensure a stable system A sample screenshot is shown below Note The module is kept in reset as...

Page 31: ...the above shown voltage divider circuitry and the transistor stage the voltage measured at the PWR_OK input pin may be only around 0 8V when the 12V is applied to the module Actively driving PWR_OK high is compliant to the COM Express specification but this can cause back driving Therefore congatec recommends driving the PWR_OK low to keep the module in reset and tri state PWR_OK when the carrier ...

Page 32: ... a result of modifications made in BIOS settings or by system software Power Supply Implementation Guidelines 12 volt input power is the sole operational power source for the conga TC87 The remaining necessary voltages are internally generated on the module using onboard voltage regulators A carrier board designer should be aware of the following important information when designing a power supply...

Page 33: ...x The Deep Sx is a lower power state employed to minimize the power consumption while in S3 S4 S5 In the Deep Sx state the system entry condition determines if the system context is maintained or not All power is shut off except for minimal logic which supports limited set of wake events for Deep Sx The Deep Sx on resumption puts system back into the state it is entered from In other words if Deep...

Page 34: ...dio controller which drives audio on integrated digital display interfaces such as HDMI and DisplayPort The conga TC87 offers the Digital Display Interface on the CD connector and supports up to three independent displays The display combination must be 2 DDI and 1 LVDS eDP For revisions equipped with optional VGA the combination must be 1x DDI Port B 1x VGA via Port C and 1x LVDS eDP The table be...

Page 35: ... HDMI interface See table 2 above for possible display combinations Consumer electronics control CEC is not supported 6 2 3 2 DVI The conga TC87 offers two DVI ports on the CD connector The DVI interfaces are multiplexed onto the Digital Display Interface of the COM Express connector Note The conga TC87 supports a maximum of 2 independent DVI displays Revisions equipped with optional VGA interface...

Page 36: ...e for possible display combinations 6 2 4 USB 3 0 The conga TC87 offers two SuperSpeed USB 3 0 ports on the CD connector These ports are controlled by an xHCI host controller provided by the Intel 8 Series PCH LP integrated in the MCP The host controller allows data transfers of up to 5 Gb s and supports SuperSpeed high speed full speed and low speed traffic Note The xHCI controller supports USB 3...

Page 37: ...t also keeps track of dynamically changing data like runtime meter and boot counter 7 3 Watchdog The conga TC87 is equipped with a multi stage watchdog solution that is triggered by software The COM Express Specification does not provide support for external hardware triggering of the Watchdog which means the conga TC87 does not support external hardware triggering For more information about the W...

Page 38: ...re their own CMOS default configuration and BIOS logo splash screen within the BIOS flash device Customized BIOS development by congatec for these changes is no longer necessary because customers can easily do these changes by themselves using the congatec system utility CGUITL 7 6 3 OEM BIOS Code With the congatec embedded BIOS it is even possible for system designers to add their own code to the...

Page 39: ...asily integrate all these features into their code The CGOS API congatec Operating System Application Programming Interface is the congatec proprietary API that is available for all commonly used Operating Systems such as Win32 Win64 Win CE Linux The architecture of the CGOS API driver provides the ability to write application software that runs unmodified on all congatec CPU modules All the hardw...

Page 40: ...includes coprocessors to calculate efficient hash and RSA algorithms with key lengths up to 2 048 bits as well as a real random number generator Security sensitive applications like gaming and e commerce will benefit also with improved authentication integrity and confidence levels 7 8 Suspend to Ram The Suspend to RAM feature is available on the conga TC87 ...

Page 41: ...rting AHCI may take advantage of performance features such as port independent DMA engines each device is treated as a master and hardware assisted native command queuing AHCI also provides usability enhancements such as Hot Plug and advanced power management 8 1 1 2 RAID The industry leading RAID capability provides high performance RAID 0 1 5 and 10 functionality on the 4 SATA ports of Intel 8 S...

Page 42: ...of active cores The amount of time the processor spends in the Intel Turbo Boost 2 Technology state depends on the workload and operating environment Any of the following can set the upper limit of Intel Turbo Boost Technology on a given workload Number of active cores Estimated current consumption Estimated power consumption Processor temperature When the processor is operating below these limits...

Page 43: ... about this subject THERMTRIP signal is used by Intel s Core i7 i5 i3 and Celeron processors for catastrophic thermal protection If the processor s silicon reaches a temperature of approximately 125 C then the processor signal THERMTRIP will go active and the system will automatically shut down to prevent any damage to the processor as a result of overheating The THERMTRIP signal activation is com...

Page 44: ...Intel 64 are not utilized 2 Compatibility Mode 64 bit operating system and 32 bit applications This mode requires all device drivers to be 64 bit The operating system will see the 64 bit extensions but the 32 bit application will not Existing 32 bit applications do not need to be recompiled and may or may not benefit from the 64 bit extensions The application will likely need to be re certified by...

Page 45: ...vendor and not congatec technical support 8 2 6 Thermal Management ACPI is responsible for allowing the operating system to play an important part in the system s thermal management This results in the operating system having the ability to take control of the operating environment by implementing cooling decisions according to the demands put on the CPU by the application The conga TC87 supports ...

Page 46: ...ndby mode is set to S3 USB hardware must be powered by standby power source Set USB Device Wakeup from S3 S4 to ENABLED in the ACPI setup menu if setup node is available in BIOS setup program In Device Manager look for the keyboard mouse devices Go to the Power Management tab and check Allow this device to bring the computer out of standby RTC Alarm Activate and configure Resume On RTC Alarm in th...

Page 47: ... the RMH is multiplexed with Port 1 of the EHCI controller and is able to bypass the RMH for use as the Debug Port The hub operates like any USB 2 0 Discrete Hub and will consume one tier of hubs allowed by the USB 2 0 Spec A maximum of four additional non root hubs can be supported on any of the PCH USB Ports The RMH will report the following Vendor ID 8087h and Product ID 8000h Routing Diagram E...

Page 48: ...ented by the chip vendors only pull ups or pull downs implemented by congatec are listed For information about the internal pull ups or pull downs implemented by the chip vendors refer to the respective chip s datasheet Table 3 Signal Tables Terminology Descriptions Term Description PU congatec implemented pull up resistor PD congatec implemented pull down resistor I O 3 3V Bi directional signal 3...

Page 49: ...n Audio Serial Data In 0 These signals are serial TDM data inputs from the three codecs The serial input is single pumped for a bit rate of 24 Mb s for Intel High Definition Audio I 3 3VSB AC 97 codecs are not supported Note Some signals have special functionality during the reset process They may bootstrap some basic important functions of the module For more information refer to section 9 5 of t...

Page 50: ...ial ATA channel 0 Receive Input differential pair I SATA Supports Serial ATA specification Revision 3 0 SATA0_TX SATA0_TX A16 A17 Serial ATA channel 0 Transmit Output differential pair O SATA Supports Serial ATA specification Revision 3 0 SATA1_RX SATA1_RX B19 B20 Serial ATA channel 1 Receive Input differential pair I SATA Supports Serial ATA specification Revision 3 0 SATA1_TX SATA1_TX B16 B17 Se...

Page 51: ..._RX3 PCIE_RX3 B58 B59 PCI Express channel 3 Receive Input differential pair I PCIE Supports PCI Express Base Specification Revision 2 0 PCIE_TX3 PCIE_TX3 A58 A59 PCI Express channel 3 Transmit Output differential pair O PCIE Supports PCI Express Base Specification Revision 2 0 PCIE_RX4 PCIE_RX4 B55 B56 PCI Express channel 4 Receive Input differential pair I PCIE Not supported PCIE_TX4 PCIE_TX4 A55...

Page 52: ...O USB 2 0 compliant Backwards compatible to USB 1 1 USB5 B39 USB Port 5 data or D I O USB 2 0 compliant Backwards compatible to USB 1 1 USB6 A37 USB Port 6 data or D I O USB 2 0 compliant Backwards compatible to USB 1 1 USB6 A36 USB Port 6 data or D I O USB 2 0 compliant Backwards compatible to USB 1 1 USB7 B37 USB Port 7 data or D I O USB 2 0 compliant Backwards compatible to USB 1 1 USB7 B36 USB...

Page 53: ...abilities I O OD 5V PU 1k2 3 3V Optional on rev C x and later VGA_I2C_DAT B96 DDC data line I O OD 5V PU 1k2 3 3V Optional on rev C x and later Table 12 LVDS Signal Descriptions Signal Pin Description I O PU PD Comment LVDS_A0 LVDS_A0 LVDS_A1 LVDS_A1 LVDS_A2 LVDS_A2 LVDS_A3 LVDS_A3 A71 A72 A73 A74 A75 A76 A78 A79 LVDS Channel A differential pairs O LVDS LVDS_A_CK LVDS_A_CK A81 A82 LVDS Channel A d...

Page 54: ...ayer I 3 3V Table 14 SPI BIOS Flash Interface Signal Descriptions Signal Pin Description I O PU PD Comment SPI_CS B97 Chip select for Carrier Board SPI BIOS Flash O 3 3VSB Carrier shall pull to SPI_POWER when external SPI provided but not used SPI_MISO A92 Data in to module from carrier board SPI BIOS flash I 3 3VSB SPI_MOSI A95 Data out from module to carrier board SPI BIOS flash O 3 3VSB SPI_CLK...

Page 55: ...0 the benefits are obvious The Push Pull output optimizes the power consumed by the fan_pwm signal without functional change Some signals have special functionality during the reset process They may bootstrap some basic important functions of the module For more information refer to section 9 5 of this user s guide Table 16 General Purpose I O Signal Descriptions Signal Pin Description I O PU PD C...

Page 56: ..._S3 A15 Indicates system is in Suspend to RAM state Active low output An inverted copy of SUS_S3 on the carrier board also known as PS_ON may be used to enable the non standby power on a typical ATX power supply O 3 3VSB SUS_S4 A18 Indicates system is in Suspend to Disk state Active low output O 3 3VSB Not supported SUS_S5 A24 Indicates system is in Soft Off state O 3 3VSB WAKE0 B66 PCI Express wa...

Page 57: ..._12V A104 A109 B104 B109 Primary power input 12V nominal All available VCC_12V pins on the connector s shall be used P VCC_5V_SBY B84 B87 Standby power input 5 0V nominal If VCC5_SBY is used all available VCC_5V_SBY pins on the connector s shall be used Only used for standby and suspend functions May be left unconnected if these functions are not used in the system design P VCC_RTC A47 Real time c...

Page 58: ...1_TX A72 eDP_TX2 LVDS_A0 B72 LVDS_B0 A18 SUS_S4 B18 SUS_STAT A73 eDP_TX1 LVDS_A1 B73 LVDS_B1 A19 SATA0_RX B19 SATA1_RX A74 eDP_TX1 LVDS_A1 B74 LVDS_B1 A20 SATA0_RX B20 SATA1_RX A75 eDP_TX0 LVDS_A2 B75 LVDS_B2 A21 GND FIXED B21 GND FIXED A76 eDP_TX0 LVDS_A2 B76 LVDS_B2 A22 SATA2_TX B22 SATA3_TX A77 eDP LVDS_VDD_EN B77 LVDS_B3 A23 SATA2_TX B23 SATA3_TX A78 LVDS_A3 B78 LVDS_B3 A24 SUS_S5 B24 PWR_OK A...

Page 59: ...100 GND FIXED B100 GND FIXED A46 USB0 B46 USB1 A101 SER1_TX B101 FAN_PWMOUT A47 VCC_RTC B47 EXCD1_PERST A102 SER1_RX B102 FAN_TACHIN A48 EXCD0_PERST B48 EXCD1_CPPE A103 LID B103 SLEEP A49 EXCD0_CPPE B49 SYS_RESET A104 VCC_12V B104 VCC_12V A50 LPC_SERIRQ B50 CB_RESET A105 VCC_12V B105 VCC_12V A51 GND FIXED B51 GND FIXED A106 VCC_12V B106 VCC_12V A52 PCIE_TX5 B52 PCIE_RX5 A107 VCC_12V B107 VCC_12V A...

Page 60: ...r the Superspeed USB data path I USB_SSRX0 C3 I USB_SSTX0 D4 Additional transmit signal differential pairs for the Superspeed USB data path O USB_SSTX0 D3 O USB_SSRX1 C7 Additional receive signal differential pairs for the Superspeed USB data path I USB_SSRX1 C6 I USB_SSTX1 D7 Additional transmit signal differential pairs for the Superspeed USB data path O USB_SSTX1 D6 O USB_SSRX2 C10 Additional r...

Page 61: ...G_RX7 PEG_RX8 PEG_RX8 PEG_RX9 PEG_RX9 PEG_RX10 PEG_RX10 PEG_RX11 PEG_RX11 PEG_RX12 PEG_RX12 PEG_RX13 PEG_RX13 PEG_RX14 PEG_RX14 PEG_RX15 PEG_RX15 C52 C53 C55 C56 C58 C59 C61 C62 C65 C66 C68 C69 C71 C72 C74 C75 C78 C79 C81 C82 C85 C86 C88 C89 C91 C92 C94 C95 C98 C99 C101 C102 PCI Express Graphics Receive Input differential pairs Note Can also be used as PCI Express Receive Input differential pairs ...

Page 62: ...EG_TX15 D52 D53 D55 D56 D58 D59 D61 D62 D65 D66 D68 D69 D71 D72 D74 D75 D78 D79 D81 D82 D85 D86 D88 D89 D91 D92 D94 D95 D98 D99 D101 D102 PCI Express Graphics Transmit Output differential pairs Note Can also be used as PCI Express Transmit Output differential pairs 16 through 31 known as PCIE_TX 16 31 and O PCIE Not supported PEG_LANE_RV D54 PCI Express Graphics lane reversal input strap Pull low ...

Page 63: ...ATA if DDI1_DDC_AUX_SEL is pulled high I O PCIE I O OD 3 3V PU 100k 3 3V DDI1_CTRLDATA_AUX is a boot strap signal see not below DDI enable strap already populated DDI1_DDC_AUX_SEL D34 Selects the function of DDI1_CTRLCLK_AUX and DDI1_CTRLDATA_AUX This pin shall have a IM pull down to logic ground on the module If this input is floating the AUX pair is used for the DP AUX signals If pulled high the...

Page 64: ...th DP3_AUX and HDMI3_CTRLCLK DP AUX function if DDI3_DDC_AUX_SEL is no connect HDMI DVI I2C CTRLCLK if DDI3_DDC_AUX_SEL is pulled high I O PCIE I O OD 3 3V Not supported DDI3_CTRLDATA_AUX C37 Multiplexed with DP3_AUX and HDMI3_CTRLDATA DP AUX function if DDI3_DDC_AUX_SEL is no connect HDMI DVI I2C CTRLDATA if DDI3_DDC_AUX_SEL is pulled high I O PCIE I O OD 3 3V Not supported DDI3_DDC_AUX_SEL C38 S...

Page 65: ... with DDI2_PAIR2 and DDI2_PAIR2 O PCIE TMDS2_DATA1 TMDS2_DATA1 D42 D43 HDMI DVI TMDS differential pair Multiplexed with DDI2_PAIR1 and DDI2_PAIR1 O PCIE TMDS2_DATA2 TMDS2_DATA2 D39 D40 HDMI DVI TMDS differential pair Multiplexed with DDI2_PAIR0 and DDI2_PAIR0 O PCIE HDMI2_HPD D44 HDMI DVI Hot plug detect Multiplexed with DDI2_HPD I PCIE PD 1M HDMI2_CTRLCLK C32 HDMI DVI I2 C Control Clock Multiplex...

Page 66: ...port of isochronous streams and secondary data Multiplexed with DDI1_PAIR0 and DDI1_PAIR0 O PCIE DP1_HPD C24 Detection of Hot Plug Unplug and notification of the link layer Multiplexed with DDI1_HPD I 3 3V PD 1M DP1_AUX D15 Half duplex bi directional AUX channel for services such as link configuration or maintenance and EDID access I O PCIE PD 100k DP1_AUX D16 Half duplex bi directional AUX channe...

Page 67: ...condary data Multiplexed with DDI3_PAIR2 and DDI3_PAIR2 O PCIE Not supported DP3_LANE1 DP3_LANE1 C42 C43 Uni directional main link for the transport of isochronous streams and secondary data Multiplexed with DDI3_PAIR1 and DDI3_PAIR1 O PCIE Not supported DP3_LANE0 DP3_LANE0 C39 C40 Uni directional main link for the transport of isochronous streams and secondary data Multiplexed with DDI3_PAIR0 and...

Page 68: ...rd logic may also implement a fault indicator such as an LED TYPE10 A97 Dual use pin Indicates to the carrier board that a Type 10 module is installed Indicates to the carrier that a Rev 1 0 2 0 module is installed PDS Not connected to indicate Pinout R2 0 TYPE10 NC PD 12V Pinout R2 0 Pinout Type 10 pull down to ground with 4 7k resistor Pinout R1 0 This pin is reclaimed from VCC_12V pool In R1 0 ...

Page 69: ...C71 PEG_RX6 D71 PEG_TX6 C17 RSVD D17 RSVD C72 PEG_RX6 D72 PEG_TX6 C18 RSVD D18 RSVD C73 GND D73 GND C19 PCIE_RX6 D19 PCIE_TX6 C74 PEG_RX7 D74 PEG_TX7 C20 PCIE_RX6 D20 PCIE_TX6 C75 PEG_RX7 D75 PEG_TX7 C21 GND FIXED D21 GND FIXED C76 GND D76 GND C22 PCIE_RX7 D22 PCIE_TX7 C77 RSVD D77 RSVD C23 PCIE_RX7 D23 PCIE_TX7 C78 PEG_RX8 D78 PEG_TX8 C24 DDI1_HPD D24 RSVD C79 PEG_RX8 D79 PEG_TX8 C25 DDI1_PAIR4 D...

Page 70: ...D D45 RSVD C100 GND FIXED D100 GND FIXED C46 DDI3_PAIR2 D46 DDI2_PAIR2 C101 PEG_RX15 D101 PEG_TX15 C47 DDI3_PAIR2 D47 DDI2_PAIR2 C102 PEG_RX15 D102 PEG_TX15 C48 RSVD D48 RSVD C103 GND D103 GND C49 DDI3_PAIR3 D49 DDI2_PAIR3 C104 VCC_12V D104 VCC_12V C50 DDI3_PAIR3 D50 DDI2_PAIR3 C105 VCC_12V D105 VCC_12V C51 GND FIXED D51 GND FIXED C106 VCC_12V D106 VCC_12V C52 PEG_RX0 D52 PEG_TX0 C107 VCC_12V D107...

Page 71: ... O PCIE I O OD 3 3V PU100k 3 3V DDI1_CTRLDATA_AUX is a boot strap signal see not below DDI2_CTRLDATA_AUX DP2_AUX HDM2_CTRLDATA C33 Multiplexed with DP2_AUX and HDMI2_CTRLDATA DP AUX function if DDI2_DDC_AUX_SEL is no connect HDMI DVI I2C CTRLDATA if DDI2_DDC_AUX_SEL is pulled high I O PCIE I O OD 3 3V PU100k 3 3V DDI2_CTRLDATA_AUX is a boot strap signal see not below Caution The signals listed in ...

Page 72: ...cycles that are not positively decoded are forwarded to the internal PCI Bus not the LPC Bus Only specified I O ranges are forwarded to the LPC Bus In the congatec Embedded BIOS the following I O address ranges are sent to the LPC Bus 2Eh 2Fh 4Eh 4Fh 60h 64h A00h BFFh C00h CFFh always used internally Parts of these ranges are not available if a Super I O is used on the carrier board If a Super I O...

Page 73: ...ote2 1Ch 02h PCI Express Root Port 2 00h Note2 1Ch 03h PCI Express Root Port 3 00h 1Dh 00h EHCI Host Controller 00h 1Fh 00h PCI to LPC Bridge 00h 1Fh 02h Serial ATA Controller 00h 1Fh 03h SMBus Host Controller 00h 1Fh 06h Thermal Subsystem 01h Note3 00h 00h PCI Express Port 0 02h Note3 00h 00h PCI Express Port 1 03h Note3 00h 00h PCI Express Port 2 04h Note3 00h 00h PCI Express Port 3 Note 1 In th...

Page 74: ...1 These interrupt lines are virtual message based 2 Interrupt used by single function PCI Express devices INTA 3 Interrupt used by multifunction PCI Express devices INTB 4 Interrupt used by multifunction PCI Express devices INTC 5 Interrupt used by multifunction PCI Express devices INTD 10 4 I C Bus There are no onboard resources connected to the I C bus Address 16h is reserved for congatec Batter...

Page 75: ... device that should be used or an option to enter the BIOS setup program 11 2 Setup Menu and Navigation The congatec BIOS setup screen is composed of the menu bar left frame and right frame The menu bar is shown below Main Advanced Chipset Boot Security Save Exit The left frame displays all the options that can be configured in the selected menu Grayed out options cannot be configured Only the blu...

Page 76: ... and time You can always return to the main setup screen by selecting the Main tab Feature Options Description Main BIOS Version no option Displays the main BIOS version OEM BIOS Version no option Displays the additional OEM BIOS version Build Date no option Displays the date the BIOS was built Product Revision no option Displays the hardware revision of the board Serial Number no option Displays ...

Page 77: ...ion Displays the processor microcode revision IGD HW Version no option Displays the version of the graphics controller IGD VBIOS Version no option Displays the video BIOS version Total Memory no option Displays the total amount of installed memory PCH Information no option subtitle Codename no option Displays the codename of the platform controller hub PCH PCH SKU no option Displays the SKU name o...

Page 78: ...ay be used by the Internal Graphics Device Memory above the fixed graphics memory will be dynamically allocated by the graphics driver according to DVMT 5 0 specification MAX Use as much graphics memory as possible Depends on total system memory installed and the operating system used see DVMT 5 0 specification Primary IGD Boot Display Device Auto LFP EFP EFP2 Select the Primary IGD display device...

Page 79: ...n brackets specifies the congatec internal number of the respective panel data set Note Customized EDID utilizes an OEM defined EDID data set stored in the BIOS flash device Backlight Inverter Type None PWM I2C Select the type of backlight inverter used PWM Use IGD PWM signal I2C Use I2C backlight inverter device connected to the video I C bus PWM Inverter Polarity Normal Inverted Select PWM inver...

Page 80: ...elect the timeout value for the POST watchdog The watchdog is only active during the power on self test of the system and provides a facility to prevent errors during boot up by performing a reset Stop Watchdog for User Interaction No Yes Select whether the POST watchdog should be stopped during the popup boot selection menu or while waiting for setup password insertion Runtime Watchdog Disabled O...

Page 81: ...e watchdog event Timeout 2 see above Selects the timeout value for the second stage watchdog event Timeout 3 see above Selects the timeout value for the third stage watchdog event Watchdog ACPI Event Shutdown Restart Select the operating system event that is initiated by the watchdog ACPI event These options perform a critical but orderly operating system shutdown or restart Note In ACPI mode it i...

Page 82: ...3E8h Set serial port base address Interrupt None IRQ3 IRQ4 IRQ5 IRQ6 IRQ10 IRQ11 IRQ14 IRQ15 Set serial port interrupt PNP ID None PNP0501 CGT0501 CGT0502 Set serial port ACPI ID Baudrate 2400 4800 9600 19200 38400 57600 115200 Set serial port initial baudrate 11 4 4 Hardware Health Monitoring Submenu Feature Options Description CPU Temperature no option Displays the actual CPU temperature in C Bo...

Page 83: ...0 192 224 248 PCI Bus Clocks Select value to be programmed into PCI latency timer register VGA Palette Snoop Disabled Enabled Enable or disable VGA palette registers snooping PERR Generation Disabled Enabled Enable or disable PCI device to generate PERR SERR Generation Disabled Enabled Enable or disable PCI device to generate SERR Generate EXCD0 1_PERST Disabled 1ms 5ms 10ms 50ms 100ms 150ms 200ms...

Page 84: ...s 4096 Bytes Set maximum read request size of PCI Express devices or allow system BIOS to select the value ASPM Disabled Auto Force L0s PCI Express Active State Power Management settings Extended Synch Disabled Enabled If enabled the generation of extended PCI Express synchronization patterns is allowed Link Training Retry Disabled 2 3 5 Defines number of retry attempts software will take to retra...

Page 85: ...4 IRQ5 IRQ6 IRQ10 IRQ11 IRQ14 IRQ15 The interrupt reserved here will not be assigned to any PCI or PCI Express device and thus maybe available for some legacy bus device Reserve Legacy Interrupt 2 same as Reserve Legacy Interrupt 1 same as Reserve Legacy Interrupt 1 11 4 5 3 PCI Express Port Submenu Feature Options Description PCI Express Port x Disabled Enabled Enable or disable the respective PC...

Page 86: ...ed Auto Gen1 Maximum speed of the PCIe port Auto Gen1 or Gen2 Gen1 2 5GT s Some older non compliant PCI Express devices will function only if Gen1 is selected Some Gen2 devices start up in Gen1 mode and then their OS driver sets them to Gen2 mode Detect Non compliant Device Disabled Enabled Try to detect also a non compliant PCI Express device If enabled POST time will be longer Extra Bus Reserved...

Page 87: ...PI Low Power S0 Idle Disabled Enabled Enable or disable ACPI Low Power S0 Idle support Native PCI Express Support Disabled Enabled Enable or disable native OS PCI Express support Native ASPM Disabled Enabled Enabled The OS will control the ASPM support of the PCI Express device Disabled The BIOS will control the ASPM support of the PCI Express device ACPI Debug Disabled Enabled Open a memory buffe...

Page 88: ...ype 10 modules use a Push Pull output for the fan_pwm signal instead of the open drain output specified in the COM Express specification Although this does not comply with the COM Express specification 2 0 the benefits are obvious The Push Pull output optimizes the power consumed by the fan_pwm signal without functional change 11 4 7 RTC Wake Submenu Feature Options Description Wake System At Fixe...

Page 89: ...her Intel VT x Technology is supported Intel SMX Technology no option Displays whether Intel SMX Technology is supported 64 bit no option Displays whether 64 bit is supported EIST Technology no option Displays whether Enhanced Intel SpeedStep Technology EIST is supported CPU C3 State no option Displays whether CPU C3 State is supported CPU C6 State no option Displays whether CPU C6 State is suppor...

Page 90: ...AES Disabled Enabled Enable or disable CPU Advanced Encryption Standard AES instructions EIST Disabled Enabled Enable or disable Enhanced Intel SpeedStep Technology EIST Energy Performance Performance Balanced Perform Balanced Energy Energy Efficient Optimize between performance and power savings Turbo Mode Disabled Enabled Enable or disable Turbo Mode Package Power Limit Lock Disabled Enabled Whe...

Page 91: ...eport to OS CPU C6 Report Disabled Enabled Enable or disable CPU C6 report to OS C6 Latency Short Long Configure Short Long latency for C6 CPU C7 Report Disabled CPU C7 CPU C7s Enable or disable CPU C7 report to OS C7 Latency Short Long Configure Short Long latency for C7 CPU C8 Report Disabled Enabled Enable or disable CPU C8 report to OS Note Not displayed supported on all Processors types CPU C...

Page 92: ...n of TDP levels base on current power and thermal delivery capabilities of the system Config TDP Lock Disabled Enabled Lock the config TDP control register TCC Activation Offset 0 50 Default 0 Offset from the Intel factory Thermal Control Circuit TCC activation temperature TCC activation will lower CPU core and graphics core frequency voltage or both The factory TCC activation temperature is norma...

Page 93: ...D Enabled Disabled Report alternate Device ID Displayed just for RAID SATA Mode Serial ATA Port 0 1 2 3 no option Displays the name of the connected Hard Disk or DVDROM when the port is enabled Empty is displayed when the port is disabled or when the port is enabled but nothing is connected to it On conga TC87 variants equipped with mainstream chipset the SATA ports 2 and 3 are not available Softw...

Page 94: ...RT volumes can span internal and external SATA eSATA drives If disabled then any RAID volume can span internal and eSATA drives Intel Smart Response Technology Disabled Enabled Enable or disable Intel Smart Response Technology Option ROM UI Delay 2 Seconds 4 Seconds 6 Seconds 8 Seconds If enabled indicates the delay of the option ROM user interface splash screen in a normal status 11 4 11 Intel R ...

Page 95: ...optical or hard disk drives SATA Port 0 Disk drive name Acoustic Mode Bypass Quiet Max Performance Acoustic noise level and performance optimization of optical or hard disk drives Bypass Use drive s preset value Quiet Drive is slower but quieter Max Performance Drive is faster but possibly noisier SATA Port 1 Disk drive name Acoustic Mode Bypass Quiet Max Performance Same as at SATA Port 0 SATA Po...

Page 96: ...abled Enabled Enable or disable EHCI USB 2 0 controller One EHCI controller must always be enabled USB2 0 Pins Routing Route Per Pin Route all Pins to EHCI Route all Pins to xHCI Route USB2 0 pins to EHCI or xHCI controller USB2 0 Port 0 Pins Route to EHCI Route to xHCI Route the respective USB2 0 port to EHCI or xHCI controller USB2 0 Port 1 Pins Route to EHCI Route to xHCI Route the respective U...

Page 97: ...k and interrupt transfers Device Reset Timeout 10 sec 20 sec 30 sec 40 sec USB mass storage device Start Unit command timeout Device Power Up Delay Selection Auto Manual Define the maximum time a USB device might need before it properly reports itself to the host controller Auto selects a default value which is 100ms for a root port or derived from the hub descriptor for a hub port Device Power Up...

Page 98: ...t USB Port 4 Disabled Enabled Enable or disable the respective USB2 0 port USB Port 5 Disabled Enabled Enable or disable the respective USB2 0 port USB Port 6 Disabled Enabled Enable or disable the respective USB2 0 port USB Port 7 Disabled Enabled Enable or disable the respective USB2 0 port USB3 0 Port 0 Disabled Enabled Enable or disable the respective USB3 0 port USB3 0 Port 1 Disabled Enabled...

Page 99: ...n of the parallel port if enabled Device Mode Standard Parallel Mode EPP Mode ECP Mode EPP Mode ECP Mode Set the parallel port mode Note This setup menu is only available if an external Winbond W83627 Super I O has been implemented on the carrier board 11 4 16 Serial Port Console Redirection Submenu Feature Options Description COM0 Console Redirection Disabled Enabled Enable or disable serial port...

Page 100: ...pport Disabled Enabled Enable VT UTF8 combination key support for ANSI VT100 terminals Recorder Mode Disabled Enabled With recorder mode enabled only text output will be sent over the terminal This is helpful to capture and record terminal data Resolution 100x31 Disabled Enabled Enables or disables extended terminal resolution Legacy OS Redirection Resolution 80x24 80x25 Number of rows and columns...

Page 101: ...ntered UEFI Driver no option Displays the UEFI Driver version Adapter PBA no option Displays the Adapter PBA Chip Type no option Displays the type of the Chip in which the Ethernet controller is integrated PCI Device ID no option Displays the PCI Device ID of the Ethernet controller Bus Device Function no option Displays the PCI Bus Device Function number of the Ethernet controller Link Status no ...

Page 102: ...cification PCIe USB Glitch W A Disabled Enabled PCIe USB glitch W A for bad USB device s connected behind PCIe PEG port USB Precondition Disabled Enabled Precondition work on USB host controller and root ports for faster enumeration xHCI Idle L1 Enabled Disabled Enable or disable xHCI Idle L1 The xHCI Idle L1 should be set to Disabled for PCH Ax stepping early prototype to work around USB3 0 hot p...

Page 103: ...om DeepSx by the assertion of GP27 pin PCIe Wake From DeepSx Disabled Enabled Wake from DeepSx by the assertion of PCIe Serial IRQ Mode Quiet Continuous Configure serial IRQ mode SB CRID Disabled Enabled Enable or disable southbridge compatible revision ID support PCH Cross Throttling Disabled Enabled Enable or disable the PCH cross throttling feature SLP_S4 Assertion Width Disabled 1 2 Seconds 2 ...

Page 104: ... link is the main but exclusively internal bus between the Processor and Platform Controller Hub PCH Memory Configuration submenu Memory configuration parameters GT Power Management Control submenu Processor Graphics Controller GT power management control options 11 5 2 1 DMI Configuration Submenu Feature Options Description DMI no option Displays the DMI bus characteristics DMI Vc1 Control Enable...

Page 105: ...cted CAUTION For congatec internal debugging only DO NOT CHANGE Custom Profile Control Submenu Configure the custom DIMM profile options CAUTION For congatec internal debugging only DO NOT CHANGE Memory Frequency Limiter Auto 1067 1333 1600 1867 2133 2400 2667 Maximum memory frequency selections in MHz Hidden if DIMM profile is set to Custom Profile DDR Reset Wait Time 0 3000000 Default 0 The amou...

Page 106: ...it Fast Exit DIMM Exit Mode control Power Down Mode No Power Down APD PPD PPD DLLoff APD PPD Auto Power Down Mode control Default is Auto when DIMM Exit Mode is set to Slow Exit and PPD when DIMM Exit Mode is set to Fast Exit Memory Remap Enabled Disabled Enable or disable memory remap above 4G GDXC Support Enabled Disabled Enable or disable GDXC support 11 5 2 3 GT Power Management Control Submen...

Page 107: ... off until the power button is pressed Turn On restores power to the computer Last State restores the previous power state before power loss occurred Note Only works with an ATX type power supply AT Shutdown Mode System Reboot Hot S5 Determines the behavior of an AT powered system after a shutdown Enter Setup If No Boot Device No Yes Select whether the setup menu should be started if no boot devic...

Page 108: ... NOT be shown during POST For UEFI OS boot the UEFI GOP driver will be installed USB Support Disabled Full Init Partial Init If set to Disabled no USB device will be available before OS boot If set to Partial Init specific USB ports devices will NOT be available before OS boot If set to Enabled all USB devices will be available during POST and after OS boot PS 2 Device Support Disabled Enabled If ...

Page 109: ...of UEFI and legacy mass storage device option ROMs Video Option ROM Launch Policy Do Not Launch UEFI ROM Only Legacy ROM Only Legacy ROM First UEFI ROM First Controls the execution of UEFI and legacy video option ROMs Other Option ROM Launch Policy UEFI ROM Only Legacy ROM Only Controls the execution of option ROMs for PCI PCI Express devices other than network mass storage or video GateA20 Active...

Page 110: ...figuration without authorization With an assigned BIOS password the BIOS prompts the user for a password on a setup entry If the password entered is wrong the BIOS setup program will not launch The congatec BIOS uses a SHA256 based encryption for the password which is more secured than the original AMI encryption The BIOS password is case sensitive with a minimum of 3 characters and a maximum of 2...

Page 111: ... enabled the UEFI firmware starts the bootloader only if the bootloader s signature has maintained integrity and also if one of the following conditions is true The bootloader was signed by a trusted authority that is registered in the UEFI database The user has added the bootloader s digital signature to the UEFI database The BIOS provides the key management setup sub menu for this purpose Note T...

Page 112: ...f POST to prevent their misuse Without this protection it would be possible for viruses or malicious programs to set a password on a drive thereby blocking the user from accessing the data Note If the user enables password support a power cycle must occur for the hard drive to lock using the new password Both user and master password can be set independently however the drive will only lock if a u...

Page 113: ...number and xx is the major and minor revision number The BV87 BIOS binary size is 16MB The BU87 BIOS binary size is 8MB 12 1 Supported Flash Devices The conga TC87 supports the following flash devices Spansion S25FL064K0SMFI01 8MB Winbond W25Q128FVSIG 16MB Winbond W25Q64CVSSIG 8MB The flash devices listed above can be used on the carrier board for external BIOS support For more information about e...

Page 114: ... Revision 1 0 LPC http developer intel com design chipsets industry lpc htm Universal Serial Bus USB Specification Revision 2 0 http www usb org home PCI Specification Revision 2 3 http www pcisig com specifications Serial ATA Specification Revision 3 0 http www serialata org PICMG COM Express Module Base Specification http www picmg org PCI Express Base Specification Revision 2 0 http www pcisig ...

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