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2017
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9.2
Boot Strap Signals
Table 35 Boot Strap Signal Descriptions
Signal
Pin # Description of Boot Strap Signal
I/O
PU/PD Comment
AC/HDA_SDOUT
A33
High Definition Audio Serial Data Out: This signal is the serial TDM data
output to the codec(s). This serial output is double-pumped for a bit rate of
48 Mb/s for High Definition Audio.
O 3.3VSB
PU 1k
3.3VSB
Bootstrap signals
SPKR
B32
Output for audio enunciator, the “speaker” in PC-AT systems
O 3.3V
PEG_LAN_RV#
D54
PCI Express Graphics lane reversal input strap. Pull low on the carier board
to reverse lane order.
13.3V
PU 10k
3.3V
DDI1_CTRLDATA_AUX-
DP1_AUX-
HDMI_CTRLDATA
D16
Multiplexed with DP1_AUX- and HDMI1_CTRLDATA.
DP AUX- function if DDI1_DDC_AUX_SEL is no connect.
HDMI/DVI I2C CTRLDATA if DDI1_DDC_AUX_SEL is pulled high.
I/O PCIE
I/O OD 3.3V
PU100k
3.3V
DDI2_CTRLDATA_AUX-
DP2_AUX-
HDM2_CTRLDATA
C33
Multiplexed with DP2_AUX- and HDMI2_CTRLDATA.
DP AUX- function if DDI2_DDC_AUX_SEL is no connect.
HDMI/DVI I2C CTRLDATA if DDI2_DDC_AUX_SEL is pulled high.
I/O PCIE
I/O OD 3.3V
PU100k
3.3V
DDI3_CTRLDATA_AUX-
DP3_AUX-
HDM2_CTRLDATA
C37
Multiplexed with DP3_AUX- and HDMI3_CTRLDATA.
DP AUX- function if DDI3_DDC_AUX_SEL is no connect.
HDMI/DVI I2C CTRLDATA if DDI3_DDC_AUX_SEL is pulled high.
I/O PCIE
I/O OD 3.3V
PU 100k
3.3V
Caution
1. The signals listed in the table above are used as chipset configuration straps during system reset. In this condition (during reset), they are
inputs that are pulled to the correct state by either COM Express™ internally implemented resistors or chipset internally implemented
resistors that are located on the module.
2. No external DC loads or external pull-up or pull-down resistors should change the configuration of the signals listed in the above table.
External resistors may override the internal strap states and cause the COM Express™ module to malfunction and/or cause irreparable
damage to the module.
