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2017
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Table 24 Gigabit Ethernet Signal Descriptions
Gigabit
Ethernet
Pin # Description
I/O
PU/PD Comment
GB
GBE0_MDI0-
GB
GBE0_MDI1-
GB
GBE0_MDI2-
GB
GBE0_MDI3-
A13
A12
A10
A9
A7
A6
A3
A2
Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate
in 1000, 100, and 10Mb/sec modes. Some pairs are unused in some modes according to the following:
I/O
Analog
Twisted pair
signals for
external
transformer.
1000
100
10
MDI[0]+/-
B1_DA+/-
TX+/-
TX+/-
MDI[1]+/-
B1_DB+/-
RX+/-
RX+/-
MDI[2]+/-
B1_DC+/-
MDI[3]+/-
B1_DD+/-
GBE0_ACT#
B2
Gigabit Ethernet Controller 0 activity indicator, active low.
O 3.3VSB
GBE0_LINK#
A8
Gigabit Ethernet Controller 0 link indicator, active low.
O 3.3VSB
GBE0_LINK100#
A4
Gigabit Ethernet Controller 0 100Mb/sec link indicator, active low.
O 3.3VSB
GBE0_LINK1000#
A5
Gigabit Ethernet Controller 0 1000Mb/sec link indicator, active low.
O 3.3VSB
GBE0_CTREF
A14
Reference voltage for Carrier Board Ethernet channel 0 magnetics center tap. The reference voltage is
determined by the requirements of the module PHY and may be as low as 0V and as high as 3.3V. The
reference voltage output shall be current limited on the module. In the case in which the reference is
shorted to ground, the current shall be limited to 250mA or less.
Not
connected
Note
1. The GBE0_LINK# output is not active during a 10 Mb connection. It is only active during a 100 Mb or 1 Gb connection. This is a limitation
of Ethernet Phy since it has only three LED outputs—ACT#, LINK100# and LINK1000#.
2. The GBE0_LINK# signal is a logic AND of the GBE0_LINK100# and GBE0_LINK1000# signals on the conga-TS175 module.
Table 25 Intel
®
High Definition Audio Link Signals Descriptions
Signal
Pin #
Description
I/O
PU/PD Comment
AC/HDA_RST#
A30
Intel
®
High Definition Audio Reset: This signal is the master hardware reset to
external codec(s).
O 3.3VSB
AC’97 codecs are not supported.
AC/HDA_SYNC
A29
Intel
®
High Definition Audio Sync: This signal is a 48 kHz fixed rate sample sync
to the codec(s). It is also used to encode the stream number.
O 3.3VSB
AC’97 codecs are not supported.
AC/HDA_BITCLK
A32
Intel
®
High Definition Audio Bit Clock Output: This signal is a 24.000MHz serial
data clock generated by the Intel
®
High Definition Audio controller.
O 3.3VSB
AC’97 codecs are not supported.
AC/HDA_SDOUT
A33
Intel
®
High Definition Audio Serial Data Out: This signal is the serial TDM data
output to the codec(s). This serial output is double-pumped for a bit rate of 48
Mb/s for Intel
®
High Definition Audio.
O 3.3VSB
AC’97 codecs are not supported.
AC/HDA_SDOUT is a boot strap signal
(see note below)
