Fusion 878A
3.0 Electrical Interfaces
PCI Video Decoder
3.3 General Purpose I/O Port
100600B
Conexant
3-11
I
Data is written to and read from the GPIO pins through the GPDATA signal.
When configured to output signals through the GPIO, information is written to a
GPDATA holding register, which is output to the pin. When configured to input
data from the GPIO, buffered data is read directly from the pin. Illustrated in
Each GPIO pin must be configured either as an input or an output according to
the 24-bit GPOE register. Each bit in the register corresponds to an output driver
for a GPIO pin. A value of 1 in the register enables the output buffer, making the
pin an output pin. A value of 0 in the register disables the output buffer, making
the pin an input pin.
To avoid any conflicts, parts will power-up with the GPOE register set to
0x000000, which means all pins are three-stated and configured as inputs.
Any information written to GPDATA[n] while GPOE[n] is low will be lost.
Take care not to enable the GPOE bits for GPIO pins, set up on the board as input
pins. If you read GPDATA[n] while GPOE[n] is enabled, the value read back will
echo what was last written to the GPDATA holding register. This will likely create
contention on the signal. Avoid enabling GPOE[n] when expecting to read an
external value on GPIO[n].
Normal mode permits PCI burst transfers by providing a 64-DWORD
contiguous address space. Only the lower 24 bits of the 32-bit PCI DWORD are
sent over the GPIO port. An interrupt may be requested through the GPIO[8] pin.
The GPINTR pin is linked to the Interrupt Status Register within the part, and
controls the GPINT bit of that register. The GPINTI and GPINTC bits provide
options for the GPINT bit. The GPINTI bit, when set, inverts the value of the
GPINTR signal immediately after the input buffer. The GPINTC bit provides a
means of registering the GPINTR input. If the GPINTC bit is low, the GPINTR
non-inverted/inverted input will go straight to the GPINT register. If GPINTC is
high, the GPINT bit changes on the rising edge of the non-inverted or inverted
GPINTR input.
Theoretically, the GPIO port can output (write) at a maximum of 11.1 MHz,
and input (read) at a maximum of 8.3 MHz. Normal mode is asynchronous, and it
is therefore difficult to ascertain a definite maximum frequency of operation.
Real world maximum frequencies will be lower than theoretical frequencies
because system configuration and PCI bus availability are limiting factors.
Figure 3-7. GPIO Normal Mode
879A_037
Video
Decoder
Scaler
Video Data
Format Converter
FIFO
DMA Controller
and PCI Initiator
Local Registers
External Circuitry
GPIO Port
24 Bits of General I/O
