Fusion 878A
3.0 Electrical Interfaces
PCI Video Decoder
3.3 General Purpose I/O Port
100600B
Conexant
3-19
3.3.7.2 Modified
SMPTE-125
The Modified SMPTE-125 interface is the same as CCIR656, but the clock runs
at 24.54 MHz, with 640 active pixels on a 780 pixel line. This clock rate
difference provides simple interface for digital cameras from Silicon Vision and
Logitech.
To properly implement a digital video input mode with CCIR656 incoming
data, several steps must be taken to set the part up to accept data:
1.
Set the signal format to CCIR656 (VSFMT[2:0] in the DVSIF register).
2.
Set the sync video reference to align with Cb, Cr, Y1, or Y0 (SVREF bits
in DVSIF register).
3.
Disable the sync output register (VSIF-ESO in the DVSIF register).
4.
Load the TG_RAM table. Place the Timing Generator Video mode into
Read/Write mode (TGC_VM bit in the TGCNTRL register). Reset the
Timing Generator Address (GPC_AR in the TGCNTRL register. Write the
LSB of the TG_RAM table first. The address will be incremented
automatically. TG_RAM maps may be obtained from your local FAE.
5.
Set the desired PLL frequency. (This is not necessary, but will provide the
correct blue screen output in the event the input is disconnected. If the
input clock is disconnected, the decoder will run off the PLL, or the XTAL
if the PLL is sleeping.)
6.
Select GPCLK as the decoder input clock. Set the GPIO_DMA_CTL
register bits [12:10] to 100 to select the SPI Input mode. The entire
decoder will now be run by the external clock.
7.
Enable the Timing Generator Video mode, by setting bit 0 of the TGCTRL
register to a logical 1.
Figure 3-12. CCIR 656 Interface to Digital Input Port
CCIR 656
Video Generator
Fusion 878A
8
Clock
DATA[7:0]
GPCLK
GPIO[7:0]
879A_044
