CompuLab Ltd.
Fitlet GPIO Connector
–
User guide
Page
9
of
9
3.2
GPIO Configuration Table
GPIO configuration table maps the available signals voltage, functionality, direction and other
characteristics in default state (power up) and BIOS configured state.
Figure 3
–
fitlet GPIO configuration table
Pin
Functionality
Voltage/Power
domain
Functionality
GPIO Direction
Pull (PU/PD)
GPIO
Voltage
Power
domain
BIOS
Default
BIOS
Default
BIOS
GPIO32
3.3V
S0
F2
In
In
PU
PU
GPIO65
3.3V
S0
F1
In
In
PU
PU
GPIO50
3.3V
S0
F2
In
Out High PU
PU
GPIO51
3.3V
S0
F2
In
Out High No Pull
PU
GPIO170
3.3V
S5
F1
In
In
PD
PD
SCLK0
3.3V
I
2
C Clock
SDATA0
3.3V
I
2
C Data
GPIO69
3.3V
F2
Out Low
PD
GPIO168
3.3V
S5
F1
In
In
PD
PD
GPIO169
3.3V
S5
F1
In
In
PD
PD
GPIO184
3.3V
S5
F1
In
In
PU
PU
COM2_RX
3.3V
3.3V
UART Rx
COM2_TX
3.3V
3.3V
UART Tx
GND
GND
Note: GPIO BIOS configuration settings are subject to changes. Please refer to up to date
document for the latest information.
Warning: Proper ESD protection required to eliminate damage when operating fitlet with
external hardware. Proper grounding required to provide stable signaling and avoid damage.
Do NOT operate the interface unless you know what you’re doing!
