Compaq Professional 5100 Supplementary Manual Download Page 7 | Manualshive

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Compaq Professional 5100 Supplementary Manual Download Page 7

T

ECHNOLOGY

B

RIEF

(cont.)

7

ECG066/1198

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memory size and evenly splitting those DIMMs between the two memory channels. Table 1 is a
DIMM configuration guide for optimizing performance of dual memory buses. The table shows
matched memory sizes on both banks. Other memory configurations are valid.

T

A B L E

1 : G

U I D E F O R

C

O N F I G U R I N G

D

U A L

M

E M O R Y

B

U S E S

T O

O

P T I M I Z E

P

E R F O R M A N C E

Memory Size

Memory Bus 1

DIMMs

Memory Bus 2

DIMMs

Optimization

Level *

32 MB

—

2 x 16 MB

1

64 MB

2 x 16 MB

2 x 16 MB

1

64 MB

—

4 x 16 MB

2

64 MB

—

2 x 32 MB

3

128 MB

4 x 16 MB

4 x 16 MB

1

128 MB

2 x 32 MB

2 x 32 MB

2

128 MB

—

4 x 32 MB

3

128 MB

—

2 x 64 MB

4

256 MB

4 x 32 MB

4 x 32 MB

1

256 MB

2 x 64 MB

2 x 64 MB

2

256 MB

—

4 x 64 MB

3

256 MB

—

2 x 128 MB

4

512 MB

4 x 64 MB

4 x 64 MB

1

512 MB

6 x 64 MB

2 x 64 MB

2

512 MB

8 x 64 MB

—

3

512 MB

—

4 x 128 MB

4

1 GB

8 x 64 MB

4 x 128 MB

1

1 GB

4 x 128 MB

4 x 128 MB

2

1 GB

8 x 128 MB

—

3

1 GB

—

4 x 256 MB

4

2 GB

4 x 256 MB

4 x 256 MB

1

2 GB

8 x 256 MB

—

2

* The degree of performance optimization is indicated by a numerical range. Level 1 represents the best performance. Levels 2,

3, and 4 indicate progressively lower performance.

The exact performance increase to be gained by optimizing the memory subsystem is highly
dependent upon the application. Some applications will see less than 1 percent benefit, while
others may see as much as 33 percent. In general, workstation applications with large data sets
(for example, MacNeil Schwendler Corporation’s NASTRAN Finite Element Analysis software)
make better use of the dual memory controllers than most PC productivity applications with small
data sets.

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Summary of Contents for Professional 5100

Page 1: ...tion DCC place growing demands on system resources increasing system bandwidth becomes a critical business issue After evaluating available system architectures Compaq determined that only a new highl...

Page 2: ...TwinTray ROMPaq LicensePaq QVision SLT ProLinea SmartStart NetFlex DirectPlus QuickFind RemotePaq BackPaq TechPaq SpeedPaq QuickBack PaqFax Presario SilentCool CompaqCare design Aero SmartStation Min...

Page 3: ...s from other architectures used in X86 systems ARCHITECTURE OVERVIEW Unlike any previous architecture used in X86 systems the new architecture being implemented by Compaq incorporates a highly paralle...

Page 4: ...sional Workstation 8000 will use the 200 MHz Pentium Pro processor with an integrated 512 KB L2 cache that runs at the core processor speed of 200 MHz The high speed processor and cache provide top pe...

Page 5: ...nd SMP aware applications Each memory bus is 144 bits wide and consists of 128 bits of data plus 16 bits for Error Checking and Correction ECC The new architecture uses buffered 60 ns Extended Data Ou...

Page 6: ...arge CAS Precharge Figure 4 Basic timeline for sequential reads from the same page of DRAM While it is fairly common for a single processor to access consecutive memory locations consecutive cycles in...

Page 7: ...MB 2 x 128 MB 4 512 MB 4 x 64 MB 4 x 64 MB 1 512 MB 6 x 64 MB 2 x 64 MB 2 512 MB 8 x 64 MB 3 512 MB 4 x 128 MB 4 1 GB 8 x 64 MB 4 x 128 MB 1 1 GB 4 x 128 MB 4 x 128 MB 2 1 GB 8 x 128 MB 3 1 GB 4 x 256...

Page 8: ...bus It is controlled by an I O cache controller When a PCI bus master requests data from system memory the I O cache controller automatically reads a full cache line 32 bytes from system memory at the...

Page 9: ...up to 1 07 GB s two to four times the bandwidth of other NT X86 systems Furthermore with dual peer PCI buses high bandwidth peripherals can be placed on separate PCI buses CPU CPU Memory Controller S...

Page 10: ...hics controller to access separate memory pools concurrently Furthermore the ELSA Gloria L 3D graphics board and the Diamond Fire GL 4000 3D graphics board available with the new Compaq workstations h...

Page 11: ...tively However a crossbar switch is an expensive solution in a system with several buses The reason is that all the buses must go into a single chip that has sufficient pins for each bus This requires...

Page 12: ...o memory bus provides bandwidth of 533 MB s Figure 9 Block diagram of the LX architecture The Highly Parallel System Architecture supports industry standard EDO memory arranged in 2 1 interleaved bank...

Page 13: ...eaks of up to 40 percent Thus PCI graphics cards still have headroom to double performance without saturating the PCI bus The dual PCI buses in the Highly Parallel System Architecture in some cases pr...

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