Compaq Professional 5100 Supplementary Manual Download Page 6

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ECHNOLOGY

RIEF

(cont.)

ECG066/1198

Because each of the two memory buses in this architecture is capable of returning data to the
processor at the full 533-MB/s speed of the processor bus, it could seem superfluous to have more
memory bandwidth than can be sent across the processor bus. One could envision the system
looking like a funnel, with the bottleneck being the processor bus. This is not true, however. To
understand why, we must look at how DRAM memory works.

Accessing DRAM memory is relatively slow, in part because the DRAM cannot transfer data
continuously. In fact, as Figure 3 illustrates, a typical memory cycle transfers data only about one
third of the time. First, the DRAM must be precharged. Second, the memory address of the data
being sought must be sent to the DRAM. Finally, the DRAM can transfer data.

CAS Precharge

Time

Send Address to RAM

Transfer Data from RAM

A Typical Memory Cycle

Figure 3. Because a DRAM memory cycle has three components, data is transferred only during about one
third of the cycle.

In some cases DRAM can transfer data faster. If two sequential cycles query addresses on the
same DRAM page, then the address for the second cycle can be sent during data transfer of the
first cycle (Figure 4). Once continuous data transfer is established on both memory buses as
illustrated in Figure 4, it is possible to achieve a peak aggregate memory bandwidth of 1.07 GB/s.

Cycle 1: Bank A

Cycle 2: Bank B

RAS Precharge

Time

Send Address to RAM

Transfer Data from RAM

Send Address to RAM

Transfer Data from RAM

CAS Precharge

...

Figure 4. Basic timeline for sequential reads from the same page of DRAM.

While it is fairly common for a single processor to access consecutive memory locations,
consecutive cycles in SMP machines are rarely sent to nearby addresses. Individual processors
typically run programs and access data from very different areas of system memory. Thus, if
processor 1 reads memory at one location and immediately thereafter processor 2 performs a read,
it will usually be to a very different address. For this reason, most memory cycles in SMP
machines look like the one in Figure 3 and transfer data only about one third of the time, yielding
a more typical memory bandwidth of 177.7 MB/s. This is true of all DRAMs and all SMP
machines; it is not unique to the new highly parallel architecture. By adding a second memory
bus, the new architecture actually doubles typical consumption of the processor bandwidth in
SMP machines:

177.7 MB/s memory bandwidth x 2 buses = 355 MB/s

To take full advantage of the two memory buses, at least two memory requests must be issued at a
time, one on each memory bus. SMP Pentium Pro processors can issue up to eight cycles at a
time, which increases the likelihood of having cycles run to both memory controllers. Because a
single processor can issue up to four cycles, the dual memory controller can also boost the
performance of a single processor.

Memory may be added to either bus individually and the system will continue to operate correctly.
For peak performance, however, equal amounts of memory should be added to both buses at the
same time. Because memory is interleaved between the two memory channels by pairs of
DIMMs, best performance results from using the maximum number of DIMMs for a given