3-10
AlphaServer DS20 Service Manual
Table 3-5 Miscellaneous Register
Name
Bits
Type
Initial
State Description
RES
<63:44>
MBZ, RAZ
0
Reserved.
DEVSUP
<43:40>
WO
0
REV
<39:32>
RO
1
Latest revision of the Cchip:
1 = Tsunami
NXS
<31:29>
RO
0
NXM source – Device that
caused the NXM.
Unpredictable if NXM not set.
0 = CPU0, 1 = CPU1.
NXM
<28>
R, W1C
0
Nonexistent memory address
detected. Sets DRIR<63> and
locks the NXS field until it is
cleared.
RES
<27:25>
MBZ, RAZ
0
Reserved.
ACL
<24>
WO
0
Arbitration clear – writing a 1
to this bit clears the ABT and
ABW fields.
ABT
<23:20>
R, W1S
0
Arbitration try – writing a 1 to
these bits sets them.
ABW
<19:16>
R, W1S
0
Arbitration won – writing a 1
to these bits sets them unless
one is already set, in which
case the write is ignored.
IPREQ
<15:12>
WO
0
Interprocessor interrupt
request – write a 1 to the bit
corresponding to the CPU you
want to interrupt. Writing a 1
here sets the corresponding bit
in the IPINTR.
IPINTR
<11:8>
R, W1C
0
Interprocessor interrupt
pending – one bit per CPU.
Pin irq<3> is asserted to the
CPU corresponding to a 1 in
this field.
