GR740-UM-DS, Nov 2017, Version 1.7
486
www.cobham.com/gaisler
GR740
Workaround:
Keep all DMA channels enabled when using the PCI DMA controller. The L2 cache
may issue RETRY responses on uncorrectable errors and the IOMMU may issue RETRY responses
when its write buffer is full.
Applicable to:
This issue is only present in silicon revision 0.
43.2.18 Force PCI AMBA multiplexing when PCIMODE_ENABLE is LOW
The PCIMODE_ENABLE signal controls the default value for the PCI controller enable bit in clock
gating unit. The enable bit from the clock gating unit in turn controls a multiplexer that disconnects
the PCI controller from the on-chip AMBA buses when the controller is disabled.
In GR740 silicon revision 0 the clock for the PCI controller can be enabled via the clock gate unit’s
register interface. This will in turn connect the PCI controller to the AMBA bus. This may lead to bus
freezes if the PCI controller memory areas are accessed since a proper PCI clock is missing.
In GR740 silicon revision 1 it is still possible to set the PCI controller’s enable bit in the clock gating
unit. This will have no effect since the internal enable signals that control clock gates and AMBA bus
multiplexers are guarded with the PCIMODE_ENABLE signal.
43.2.19 Weak pull-downs on TESTEN, DSU_EN, and JTAG_TRST
GR740 silicon revision 1 has internal weak pull-down added to the signals TESTEN, DSU_EN and
JTAG_TRST. This is a safety precaution and board designers should still properly connect these sig-
nals to ground.
43.2.20 Additional fields in register for bootstrap signals.
The external signals JTAG_TRST, DSU_EN, BREAK, and PLL_BYPASS[2:0] have been added to
the register for bootstrap signals in GR740 silicon revision 1. See section 28.3.
43.2.21 LEON4 direct cache replacement policy implementation
The LEON4 cache replacement policy is dynamically configurable and by default set to least-
recently-used (LRU). If a processor was reconfigured to use direct-mapped policy then the selection
of address bits to select the cache way was done incorrectly. The effect was that only one way was
used and the cache size was reduced to 1/4 of the total size. Correct operation is still maintained, but
both the instruction and data caches are reduced to 4 KiB in size.
Workaround:
None.
Applicable to:
These limitations are only present in silicon revision 0.
43.2.22 SDRAM controller bus parking functionality
GR740 silicon revision 1 adds bus parking functionality to the SDRAM controller. See section 10.6.2.
43.2.23 Missing SpaceWire router AMBA configuration port registers
The SpaceWire router AMBA configuration port in silicon revision 0 mapped a too small memory
space for all router registers to be accessible. Silicon revision 1 expands the address space used for the
router’s AMBA ports. The registers do not add functionality but group fields together for conve-
nience. See sections 2.3 and 13.5.3.
Workaround:
None.
Applicable to:
These limitations are only present in silicon revision 0.
