GR740-UM-DS, Nov 2017, Version 1.7
39
www.cobham.com/gaisler
GR740
4.5
PLL control and configuration
Each PLL is put in power down mode whenever either:
•
The master reset signal SYS_RESETN is asserted
•
The PLL reconfiguration is commanded to reprogram the PLLs
•
The PLL is set to be bypassed using the PLL_BYPASS bootstrap signal
The rest of the PLL configuration is controlled by the PLL reconfiguration unit. When SYS_RESETN
is asserted this will be reset asynchronously to the default configuration. The reconfiguration unit can
then be reprogrammed to other PLL configurations via the general purpose register bank interface
(see section 30.2.4).
The configuration values tabulated below are the only supported configurations, other configurations
are invalid and may lead to malfunction. Note also that when overclocking the device by exceeding
the maximum clock frequencies given in the datasheet, correct functionality is not guaranteed and
power consumption may exceed typical values.
Table 30.
Supported SYSPLL configurations
SYSPLL
Config word
SYS_CLK
Input range
System clock
Memory clock
if
MEM_CLKSEL=LOW
Comment
000010101
40-85 MHz (50 MHz
nom)
5 x SYS_CLK
(250 MHz nom)
1 x SYS_CLK
Default configuration
000001100
33.3-70 MHz
6 x SYS_CLK
1 x SYS_CLK
000001010
25-53 MHz
8 x SYS_CLK
2 x SYS_CLK
Table 31.
Supported MEMPLL configurations
MEMPLL
Config word
MEM_EXTCLOCK
Input range
Memory clock if
MEM_CLKSEL=HIGH
Comment
000001010
25-53 MHz
2 x MEM_EXTCLK
Default configuration
Table 32.
Supported SPWPLL configurations
SPWPLL
Config word
SPW_CLK
Input range
SpaceWire clock
Comment
000010000
25-53 MHz
8 x SPW_CLK
Default configuration
000001100
33.3-70 MHz
6 x SPW_CLK
