COBHAM GR716, Advanced Data Sheet And User’S Manual, Page: 452 / 547

GR716-DS-UM, May 2019, Version 1.29 455 www.cobham.com/gaisler
GR716
45.8 Registers
The core is programmed through registers mapped into APB address space.
45.8.1
Table 611.
0x00 - CTRL - Control register
Control Register
Table 610.
APB registers
APB address offset Register
0x00 Control register
0x04 Status register
0x08 Transmit register
0x0C Nominal receive register
0x10 Redundant receive register
0x14 Interrupt enable register
0x18 Interrupt register
0x1C Reserved
0x20 SPI2 control register
0x24 SPI2 time1 register
0x28 SPI2 time2 register
0x2C SPI2 config address write register
0x30 SPI2 config address read register
31 24 23 13 12 8 7 6 5 4 3 2 1 0
Key R WLEN IAMBA CPHA CPOL REV R RESET ENR ENN
0 0 0x0F 0 0 0 1 0 0 1 1
w r rw rw rw rw rw r rw rw rw
31 Safety code (KEY) - Must be 0x68 when writing, otherwise register write is ignored
23 : 13 RESERVED (R) - Read as zero and should be written to zero to ensure forward compatibility.
12 : 8 Word length (WLEN) - The value of this field determines the length in bits of a transfer on the SPI
bus. Valid values are 0x03 to 0x1F
Word length is WLEN+1, allows words of length 4-32 bits.
7 AMBA Interrupt enable (IAMBA) - If set, AMBA interrupt generation is enabled for the events that
are individually maskable by the Interrupt enable (INTE) register
6 Clock phase (CPHA) - When CPHA is ‘0’ data will be read on the first transition of SCK. When
CPHA is ‘1’ data will be read on the second transition of SCK.
5 Clock polarity (CPOL) - Determines the polarity (idle state) of the SCK clock.
4 Reverse data (REV) - When this bit is ‘0’ data is transmitted LSB first, when this bit is ‘1’ data is
transmitted MSB first.
3 RESERVED (R) - Read as zero and should be written to zero to ensure forward compatibility.
2 Reset (RESET) - Resets all the registers in the core except time registers (TIME1, TIME2) and core
enable registers (ENN and ENR).
1 Enable redundant port transfer (ENR) - Enable bit for redundant port transfer.
0 Enable nominal port transfer (ENN)- Enable bit for nominal port transfer.