Cmsemicon CMS80F731 Series, Reference Manual

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1.00
CMS80F731x Reference Manual
17.5.9
PWM Counter Mode Control Register PWMCNTM
F127H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PWMCNTM -- -- PWM5CNTM PWM4CNTM PWM3CNTM PWM2CNTM PWM1CNTM PWM0CNTM
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Bit7~Bit6 -- Reserved, must be 0.
Bit5~Bit0 PWMnCNTM: PWM channel n counter mode control bit (n=0-5);
1= Auto loading mode;
0= One-shot mode.
17.5.10
PWM Counter Enable Control Register PWMCNTE
F126H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PWMCNTE -- -- PWM5CNTE PWM4CNTE PWM3CNTE PWM2CNTE PWM1CNTE PWM0CNTE
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Bit7~Bit6 -- Reserved, must be 0.
Bit5~Bit0 PWMnCNTE: PWM channel n counter enables control bits (n=0-5);
1= PWMn counter on (PWMn starts output);
0= The PWMn counter stops (the software writes 0 and the counter stops and clears the
counter value).
(The brake triggers the bit hardware to clear 0; Single-shot mode completes the bit
hardware clearance 0)
17.5.11
PWM Counter Mode Control Register PWMCNTCLR
F128H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PWMCNTCLR -- -- PWM5CNTCLR PWM4CNTCLR PWM3CNTCLR PWM2CNTCLR PWM1CNTCLR PWM0CNTCLR
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Bit7~Bit6 -- Reserved, must be 0.
Bit5~Bit0 PWMnCNTCLR: PWM channel n counter clear control bit (n=0-5) (hardware automatic zeroing);
1= PWMn counter clears;
0= Writing 0 is invalid.
17.5.12
PWM Cycle Data Register Low 8 Bits PWMPnL (n=0-5)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PWMPnL
PWMPnL7 PWMPnL6 PWMPnL5 PWMPnL4 PWMPnL3 PWMPnL2 PWMPnL1 PWMPnL0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Registers PWMPnL (n=0-5) Address: F130H, F132H, F134H, F136H, F138H, F13AH.
Bit7~Bit0 PWMPnL<7:0>: The PWM channel n-period data register is 8 bits lower.