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CMS80F731x Reference Manual
15.3 Feature Description
After writing the CRCIN register, a system clock is passed to save the CRC operation result to the CRCDL/CRCDH register.
If necessary, the data of the previous operation must be read before writing, otherwise it will be overwritten by the new operation
result.
For example, send the data "12345678H", write the value to the CRCN register in the order of "12H", "34H", "56H", "78H",
read from the CRCRDL/CRCDH register as CRCDL=0xF0, CRCDH=0x67, that is, the result of the CRC operation in the bit
order of the data "12345678H" is 0x67F0. Register operation is as follows:
CRCIN=0x12;//First number sent
CRCIN=0x34;//Send the second number
CRCIN=0x56;//Send the third number
CRCIN=0x78;//Fourth number sent
resl=CRCDL;//Read the 8 bits lower of the CRC operation result to the variable resl
resh=CRCDH;//Read the CRC operation result by bits 8 to the variable resh
