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CMS80F731x Reference Manual
14.
Baud Rate Timer (BRT)
14.1 Overview
The chip has a 16-bit baud rate timer BRT, which mainly provides a clock for the UART module.
14.2 Related Registers
14.2.1
BRT Module Control Register BRTCon
F5C0H
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
BRTCON
BRTEN
--
--
--
--
CnNS0
CnPS1
CnPS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value
0
0
0
0
0
0
0
0
Bit7
BRTEN:
BRT timer enable bit;
1=
Enable;
0=
Disable.
Bit6~Bit3
--
Reserved, both 0;
Bit2~Bit0
BRTCKDIV<2:0>
BRT timer prescale selection bit;
000=
Fsys/1;
001=
Fsys/2;
010=
Fsys/4;
011=
100=
101=
110=
111=
Fsys/8;
Fsys/16;
Fsys/32;
Fsys/64;
Fsys/128.
14.2.2
The BRT Timer Data is Loaded With a Low 8-bit Register BRTDL
F5C1H
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
BRTDL
BRTDL7
BRTDL6
BRTDL5
BRTDL4
BRTDL3
BRTDL2
BRTDL1
BRTDL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value
0
0
0
0
0
0
0
0
Bit7~Bit0
BRTDL<7:0>:
BRT timer load value 8 bits lower;
14.2.3
The BRT Timer Data is Loaded With a High 8-bit Register BRTDH
F5C2H
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
BRTDH
BRTDH7
BRTDH6
BRTDH5
BRTDH4
BRTDH3
BRTDH2
BRTDH1
BRTDH0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value
0
0
0
0
0
0
0
0
Bit7~Bit0
BRTDH<7:0>:
BRT timer load value 8 bits higher;