BAT32G1x9 user manual | Chapter 20 Serial interface IICA
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Rev.1.02
STCFn (bit7 of the IICFn register) can be used to confirm whether a start condition was generated or the
request was rejected. Because it takes 5 fMCKs from the STTn bit "1" to the STCFn position "1" The time of the
clock, so this time must be ensured by the software.
Note: n=0,1
20.5.15
Other considerations
(1) The case where the STCENn bit is "0"
Just after
I2C
is allowed to run (IICEn=1), it is considered a communication state (IICBSYn=1)
regardless of the actual bus state. To perform master communication in a state where no stop
condition is detected, the stop condition must be made and the master communication must be
performed after the bus is released. For multi-master, master communication cannot occur in a state
where the bus is not released (no stop condition detected). Generate stop conditions in the following
order:
(1) Set IICA control register n1 (IICCTLn1).
(2) Set bit7 (IICEn) of the IICA control register n0 (IICCTLn0) to "1".
(3) Set the bit0 (SPTn) of the IICCTLn0 register to "1".
(2) The case where stcenn bit is "1"
Just after
I2C
is allowed to run (IICEn=1), it is considered a release state (IICBSYn=0,1) regardless
of the actual bus state. Therefore, when generating the first starting condition (STTn=1), in order not
to disrupt other communications, it is necessary to confirm that the bus has been released.
(3) I
2
C communication with other devices is ongoing
When the SDAAn pin is low and the SCLAn pin is high, I2C macros are considered SDAAn citations
if
I2C
is allowed to run and participate in communication in the middle the foot changes from high to
low (start condition detected). If the value on the bus is recognized as an extension code at this point,
a reply is returned that interferes with I2C communication with other devices. To avoid this, I
2
C must
be started in the following order:
(1) Clear the bit4 (SPIEn) of the IICCTLn0 register to "0" to disable the generation of an interrupt request signal
(INTIICAn) when a stop condition is detected.
(2) Set the bit7 (IICEn) of the IICCTLn0 register to "1", allowing
I2C
to run.
(3) Wait for the start condition to be detected.
(4) IICCTLn0 is placed before returning to the reply (within 4 to 72 f
MCK
clocks after the IICEn
position "1"). The bit6 (LRELn) of the register is placed "1", forcing the detection to be invalid.
(4) After setting the STTn bits and SPTn bits (bit1 and bit0 of the IICCTLn0 register), it is forbidden to
clear "0" Reposition before.
(5) If a communication appointment is made, the SPIEN bit (bit4 of the IICCTLn0 register) must be placed
at "1" to generate an interrupt request when a stop condition is detected. After an interrupt request is
generated, the transmission begins by writing communication data to the IICA shift register n (IICAn).
If no interruption occurs when a stop condition is detected, it stops in the waiting state because no
interrupt request is generated when communication begins. However, when the MSTSn bit (bit7 of
the IICA status register n (IICSn)) is detected by software, There is no need to place the SPIEn
position "1".
Note: n=0,1
