BAT32G1x9 user manual | Chapter 20 Serial interface IICA
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Rev.1.02
Hi-Z
Hi-Z
20.5.12
arbitration
When multiple master devices generate start conditions at the same time (in the case of STTn position "1"
before the STDn bit becomes "1"), the communication of the master device is carried out while adjusting the clock until
the data is different. This run is called quorum.
When the arbitration fails, the master device that fails the arbitration places the arbitration failure flag (ALDn) of
the IICA status register n (IICSn) to "1" and places the SCLAn Both the line and the SDAAn line are placed in a high
impedance state, releasing the bus.
In the event of the next interrupt request (e.g., a stop condition is detected at the 8th or 9th clock), the ALDn bit
is "1" via software
to detect the failure of the quorum.
For the timing of interrupt requests, please refer to "Generation Timing and Waiting Control for Interrupt
Requests (INTIICAn) in 14.5.8".
Note: STDn:
Bit1
of
the IICA
status register
n
(IICSn
).
STTn:
Bit1
of
IICA
control register
n0
(IICCTLn0
).
Figure 20-19
Arbitration timing example
SCLAn
SDAAn
SCLAn
SDAAn
SCLAn
SDAAn
Note: n=0,1
Master
Device 1
Master
Device 2
Conveyor
line
