BAT32G1x9 user manual | Chapter 20 Serial interface IICA
763 / 1149
Rev.1.02
20.5.11
Extension code
(1) When the high 4 bits of the receiving address are "0000" or "1111", as the received extension code, the
extended code receive flag (EXCn) is set to "1", and in the 8th The falling edge of the clock generates an
interrupt request (INTIICAn).
Does not affect local station addresses stored in slave address register n (SVAn).
(2) When the SVAn register is set to "11110xx0", if "11110xx0" is sent from the master device via a 10-bit
address, the following assertion occurs. However, an interrupt request (INTIICAn) is generated on the falling
edge of the 8th clock.
•
High 4 bits data is the same: EXCn=1
•
7 bits of data are the same: COIn=1
Note: EXCn:
bit5
of
the
IICA
status register
n
(IICSn
).
COIn:
Bit4
of
IICA
status register
n
(IICSn
).
(3) The processing after an interrupt request occurs depending on the subsequent data of the extension code
and is processed by software. If an extension code is received while the slave is running, it is participating in
the communication even if the addresses are different. For example, if you do not want to run as a slave
after receiving an extension code, you must set bit6 (LRELn) of the IICA control register n0 (IICCTLn0). "1"
to enter the standby state for the next communication.
Table 20-3 Bit definitions of the main extension codes
The slave address
R/Wbit
illustrate
0000000
0
Full call address
11110xx
0
Designation of a 10-bit subordinate address (when the address is authenticated).
11110xx
1
The designation of a 10-bit Slave address (when a read command is issued after
the address is the same).
Remarks: 1
For extension codes other than those listed above, please refer to
the
I2C-bus
datasheet
issued by
NXP.
2.n=0,1
