BAT32G1x9 user manual | Chapter 10 Timer M
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Rev.1.02
10.6 Timer M interrupt
Timer M generates timer M i (i=0, 1) interrupt requests from each of the six interrupt sources of timer M 0
and timer M1. The associated registers for the timer M interrupt are shown in Table 10-18, and the block
diagram of the timer M interrupt is shown in Figure 10-63.
Table 10-18
Timer M interrupt related registers
Status register for timer M
Interrupts of timer M enable
registers
Interrupt request flag
(Register)
Interrupt mask flag
(Register)
Timer M0
TMSR0
TMIER0
TMIF0 (IF2H)
TMMK0 (MK2H)
Timer M1
TMSR1
TMIER1
TMIF1 (IF2H)
TMMK1 (MK2H)
Figure 10-63
Block diagram of timer M interrupt
Timer Mi
Timer Mi interrupt request
i = 0
、
1
IMFA
、
IMFB
、
IMFC
、
IMFD
、
OVF
、
UDF
：
TMSri register bits
IMIEA
、
IMIEB
、
IMIEC
、
IMIED
、
OVIE
：
TMIERi register bits
IMFA bit
IMIFA bit
IMFB bit
IMIEB bit
IMFC bit
IMIEC bit
IMFD bit
IMIED bit
UDF bit
OVF bit
OVIE bit
