Cmsemicon BAT32G1 9 Series, User Manual

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BAT32G1x9 user manual | Chapter 24 Enhanced DMA
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24.5.3 The number of execution clocks for the DMA
The execution of the DMA at startup and the number of clocks required are shown in Table 24-9.
Table 24-9 execution at startup and the number of clocks required
Read vector
Control data
Read the data Write data
read Write back
1 4
Note 1 Note 2 Note 2
Note 1 For the number of clocks required to write back control data, refer to "Table 24-10 number
of clocks required to write back control data".
2. For the number of clocks required to read and write data, please refer to "Table
24-11 number of clocks required to read and write data".
Table 24-10 number of clocks required to write back control data
Settings of the DMACR
registers Address
settings
Controls the writeback of registers
The
number
of
clocks
DAMOD SAMOD RPTSEL MODE
source target
DMACTj
register
DMRLDj
register
DMSARj
register
DMDARj
register
0 0 X 0
fixed fixed
Write
back Write
back Do not
write
back Do not
write
back
1
0 1 X 0
Increa
sing
fixed
Write
back Write
back Write
back Do not
write
back
2
1 0 X 0 fixed
Increa
sing Write
back Write
back Do not
write
back Write
back
2
1 1 X 0
Increa
sing Increa
sing Write
back Write
back Write
back Write
back
3
0 X 1 1
Duplica
te
areas
fixed
Write
back Write
back Write
back Do not
write
back
2
1 X 1 1
Increa
sing Write
back Write
back Write
back Write
back
3
X 0 0 1 fixed
Duplica
te
areas Write
back Write
back Do not
write
back Write
back
2
X 1 0 1
Increa
sing Write
back Write
back Write
back Write
back
3
Note j=0~39, X: "0" or "1"
Table 24-11 number of clocks required to read and write data
Execution
status
RAM Code flash Data flash
Special function
registers
(SFR)
Extended Special Function Register
(2ndSFR).
No waiting await
Read the
data
1 2 4 1 1
1+ Wait for the
number of bets
Write data
1
— —
1 1
1+ Wait for the
number of bets