BAT32G1x9 user manual | Chapter 24 Enhanced DMA
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Rev.1.02
24.4 Operation of the DMA
Once the DMA is started, the control data is read from the DMA control data area, the data is
transmitted according to this control data, and the control data after the data transmission is written back to
the DMA control data area. It can save 40 sets of control data to the DMA control data area and transmit 40
sets of data. The transmission modes have normal mode and repeat mode, and the transmission size has 8-
bit transmission, 16-bit transmission and 32-bit transmission. Passes 1 when the CHNE bit of the DMCRj
(j=0~39) register is "1" (allow chain transfer is allowed). A boot source reads multiple control data for
continuous data transfer (chain transfer).
The 32-bit DMSARj register and the 32-bit DMDARj register specify the transmit source and destination
addresses, respectively. After data transfer, increment or fix the values of the DMSARj register and the
DMDARj register according to the control data.
24.4.1
Startup Source
The DMA is initiated by the interrupt signal of the peripheral function, and the interrupt signal to start the
DMA is selected through the DMAENi (i=0~4) register. When the data transmission (in the case of chain
transmission, continuous initial transmission) is set to the DMAENi0~DMAENi7 position of the corresponding
DMAENi register in the DMA operation "0" (disables startup).
•
In normal mode, a DMACTj (j=0~39) register is transferred to "0".
•
In repeat mode, the RPTINT bit of the DMACRj register is "1" (interrupts are allowed) and the
DMACTj register becomes "0" Of.
The internal flowchart of the DMA is shown in Figure 24-16.
Figure 24-16
DMA's internal operating flowchart
DMA start source triggers
read vector
branch (1)
CHNE=1
？
Yes
No
Yes
No
transmit data
read control data
CHNE=1
？
No
end
Yes
write '0' to
DMAENi0~DMAENi7 bits,
generate interrupt request
write back control data
CHNE=1
？
write back control data
write back control data
transmit data
read control data
transmit data
read control data
CHNE=1
？
No
Yes
write back control data
end
No
Yes
(note)
branch (1)
If it is following condition, then interrupt request generates after DMAENi0 ~ DMAENi7
bit are written with '0'.
in normal mode, perform DMACTj(j=0~39) register from '1' to '0' transfer.
In repeat mode, RPTINT bit as '1' and perform DMACTj register from '1' to '0' transfer.
Remark:
DMAENi0~DMAENi7
：
DMAENi(i=0~4)register bit
RPINT
，
CHNE
：
DMACRj(j=0~39) register bits
interrupt handling
Note: In data transfer initiated through the allow chain transfer (CHNE=1) setting, no "0" is written to
DMAENi0~DMAENi7 bits and no interrupt request is generated.
