AN201
Rev 1.5 | 65/91
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1
2
3
4
5
6
7
8
9
10
VDD
POR_RSTN
BOOT_EN
PWRTE
BOOT_END
PWRT_OV
MCLRB
SYS_RSTN
4ms delay
PWRT,64ms
Figure 20. Power-on Reset without MCLRB
VDD
Internal reset
T
BOR
≈
8ms
Figure 21. BOR Reset
Notes:
1.
After POR or BOR, if PWRTEB (UCFG0.4) is low, PWRT is active, which keeps 2048 internal slow clock cycles, about 64
ms.
2.
The TBOR time is about 157 us.
3.
After the voltage is restored to normal, the internal reset will not be released immediately, but wait for about 8 ms instead.
Table 87. Timeout in Various Cases
Oscillator
configuration
Power-on Reset
Brown-out Reset
Sleep Wake-up
/PWRTEB=0
/PWRTEB=1
/PWRTEB=0
/PWRTEB=1
INTOSC
TPWRT
-
TPWRT
-
-
