AN201
Rev 1.5 | 63/91
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6.1 Power-on Reset (POR)
The on-chip POR circuit will keep the chip in the reset state until VDD reaches a high enough level. To use the on-chip POR
function, users can simply set a resistor between the /MCLR and the VDD with no need for an external RC Reset circuit. However
it requires the VDD rising time remains the maximum. When power-on completes, the system reset will not be released
immediately. There is a delay time for about 4 ms, during which the digital circuit keeps in the reset state.
6.2 MCLR External Reset (MCLR)
VDD
/MCLRB
100R
1K
0.1uF
Figure 18. External Reset Reference Circuit Diagram
The chip's CONFIG OPTION register (UCFG0) has a MCLRE enabling bit. When this bit is 0, the reset signal is generated inside
the chip. When this bit is 1, the PA5/MCLR pin of the chip becomes the external reset pin. In this mode, the /MCLR pin has a
weak pull-up for VDD.
6.3 Power-up Timer (PWRT)
PWRT provides a fixed 64 ms timing (in normal case) for power-on reset and brown-out reset. This timer is driven by an internal
slow clock. The chip keeps in the reset state before the timeout of the timer. This time ensures that VDD will rise to a sufficiently
high voltage to make the system operate properly. PWRT can also be enabled by the system CONFIG register (UCFG0). When
the low voltage reset function is enabled, users should also enable PWRT. The PWRT timing is triggered by a VDD voltage
exceeding the VBOR threshold. It is also important to know that the actual time changes with temperature and voltage as it is
driven by the internal slow clock drive, thus this time is not a precise parameter.
6.4 Brown-out Reset / Low Voltage Reset
The low voltage reset refers to the reset occurring when the power supply voltage is lower than the VBOR threshold voltage,
which is controlled by UCFG1<1:0> bit. However, the low voltage reset may not occur when the VDD voltage is lower than VBOR
and the time does not exceed TBOR. The VBOR voltage needs to be calibrated before the chip shipping. The calibration can be
fulfilled by writing the internal calibration register through the serial port. If the BOR (brown-out reset) is enabled
(UCFG1<1:0>=00), it does not have the requirement on the maximum VDD voltage rising time. The BOR circuit will control the
chip in the reset state until the VDD voltage exceeds the VBOR threshold voltage. It is important to know that the POR circui t
does not generate a reset signal when the VDD is lower than the threshold on which the system can operate normally. If the reset
signal is generated by the BOR circuit, the VDD voltage must keep for more than 100 us at the VSS level.
