AN201
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Modify PCL
Any instruction execution with PCL as the target register will cause the program counter PC<10:8> bits to be replaced by the
PCLATH register content. Therefore the entire contents of the program counter can be changed by writing the desired high 3 bits
to the PCLATH register.
The LJUMP instruction calculation is achieved by adding an offset to the program counter (ADDWR PCL). Users should pay
more consideration when need to jump into the look-up table or the program branch table (namely, calculate the LJUMP).
Assuming that the PCLATH is set as the start address of the table and the table length is greater than 255 instructions or if the
lower 8 bits of the memory address rolls over from 0xFF to 0x00 within the table, the PCLATH must be increased by 1.
4.1.32 INDF and FSR Register
INDF is not a physical register, therefore addressing the INDF will cause an indirect addressing with an addressable address
range of 0 ~ 255. Any instruction using the INDF register actually accesses the unit that the file selection register FSR poi nts to.
Reading the INDF indirectly will return 0. Writing the INDF indirectly will cause the control operation (It may affect the state flag
bit).
