AN201
Rev 1.5 | 54/91
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UCFG2, PROM address 0x2002
Table 85. UCFG2 Configuration Register
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
UCFG2
-
-
-
-
LVDS<3:0>
Table 86. UCFG2 Bit Function Description
4.1.31 PCL and PCLATH
The program counter (PC) is 11-bit. The lower 8 bits are from the PCL register, which are a readable and writable register. The
higher 3 bits (PC<10:8>) are from the PCLATH, which cannot be read and written directly. Upon reset, the PC will be cleared to 0.
The 2 situations for the PC loading are shown in the below figure. It should be notified that, for the LCALL and LJUMP instructions
on the right side of the figure, PCLATH is not required since the operating code in the instructions is 11-bit, and the chip PC is
exactly 11-bit.
10
8 7
0
/
PCLATH<2:0>
/
ALU结果
3
8
PCH
PCL
PCLATH
10
8 7
0
/
OPCODE<10:0>
11
PCH
PCL
PCLATH
Instruction with PCL as Instruction Target LJUMP and LCALL Instruction
Figure 12. PC Loading in Different Situations
1:0
LVDEN<1:0>
Low voltage reset selection bit
00 = enable the low voltage reset
Others = disable the low voltage reset
Bit
Name
Function
7:4
-
Reserved bit
3:0
LVDS[3:0]
Low voltage reset threshold selection
Value
Voltage
0010
1.8V
0011
2.0V
0100
2.2V
0110
2.8V
Others
Reserved
