AN201
Rev 1.5 | 52/91
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Table 78. EECON1 Bit Function Description
4.1.29 EECON2 (Addr:0x9D)
Table 79. EECON2 Register
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
EECON2
-
-
-
-
-
-
-
WR
Reset
-
-
-
-
-
-
-
0
Type
-
-
-
-
-
-
-
RW
Table 80. EECON2 Bit Function Description
4.1.30 Configuration Register UCFGx
The software cannot access UCFG0, UCFG1 and UCFG2. They can only be written by the hardware (programming) in the power
up process.
UCFG0, PROM address 0x2000
Table 81
. UCFG0 Configuration Register
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
UCFG0
-
CPB
MCLRE
PWRTEB
WDTE
FOSC<2:0>
Bit
Name
Function
5,4,2
WREN<2:0>
Data EEPROM write operation enabling bit.
111 = enable programming EEPROM by software. Each bit will restore to 0 automatically
after programming completes.
Other values = disable programming EEPROM by the software
3
WRERR
Data EEPROM write operation error flag bit.
1 = write operation is terminated due to WDT or external reset occurring during the
EEPROM programming period.
0 = write operation completes normally during the EEPROM programming period.
0
RD
Data EEPROM read operation control bit. The bit is write-only. It will return always 0 if it is
read.
1 = initiate a data EEPROM read period
0 = does not initiate read
Bit
Name
Function
0
WR
Data EEPROM write operation control bit.
Read operation, 1= Data EEPROM is in the programming period
0= Data EEPROM is not in the programming period
Write operation, 1= initiates a data EEPROM programming period
0= does not provide the function
