CMT2380F64
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Input capture
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Output comparision
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Break signal input
◆
Supports incremental (quadrature) encoder and Hall sensor circuits for positioning
◆
Trigger input as an external clock or current management by cycle
In debug mode, the counter can be frozen and the PWM outputs are disabled, thereby cutting off the switches
controlled by these outputs. Many of the functions are the same as the standard TIM timer, and they also have the
same internal structure, so the advanced control timer can operate in collaboration with the TIM timer through the
timer link function to provide the synchronization or event link function.
5.10.5
Systick
This timer is specific used for real -time operating system and can also be used as a standard decrement counter.
It has the following characteristics:
◆
24 bit decrement counter
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Automatic reload function
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A maskable system interrupt can be generated when the counter is 0
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Programmable clock source
5.10.6
Watchdog Timer (WDG)
Two watchdogs are supported, Independent Watchdog (IWDG) and Window Watchdog (WWDG).Two watchdogs
provide increased security, timing accuracy and flexibility in use.
◆
Independent watchdog
（
IWDG
）
The independent watchdog is based on a 12-bit decline counter and an 8-bit prescaler, driven by an independent low- speed RC
oscillator that remains effective in the event of a master clock failure and operates in STOP mode. Once activated, IWDG
generates a reset when the counter counts to 0x000if the dog is not fed within the set time (clearing the watchdog counter). It can
be used to reset the entire system in the event of an application problem, or as a free timer to provide timeout management for the
application. The option byte can be configured to be software or hardware enabled watchdog. Reset and low power wake-up are
available.
◆
Window watchdog
（
WWDG
）
Window watchdogs are usually used to monitor software failures caused by external interference or unforeseen logic conditions
that cause the application to deviate from the normal operating sequence. Unless the value of the down counter is refreshed
before the T6 bit becomes 0, the watchdog circuit will generate an MCU reset when the preset time period is reached. Before t he
down counter reaches the window register value, if the 7-bit down counter value (in the control register) is refreshed, an MCU reset
will also be generated. This indicates that the down counter needs to be refreshed in a limited time window.
Main features:
◆
WWDG is driven by the clock after the APB 1 clock is divided;
◆
Progranmable free running decrement counter;
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Conditional reset;
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When the decrement counter value is less than 0x40
，
(if the watchdog is started) a reset is generated;
◆
Reset when the decrement counter is reloaded outside the window (if the watchdog is activated);
◆
If the watchdag is enabled and interrupts are allowed, an early wake-up interrupt (EWI) is generated when the
decrements counter equals 0x40, which can be used to reload the counter to aviod a WWDG reset.
5.11 I2C Bus Interface
Two independent I2C bus interfaces that provide multi-host functionality to control all I2C bus specific timing, protocol,
mediation, and timing.Supports multiple communication rate modes (up to 1MHz), supports DMA
operation, and is compatible with SMBUS 2.0.The I2C module has a variety of uses, including CRC code generation and
