CMT2380F17
Rev0.1 | 324/347
www.cmostek.com
30.5
Auxiliary SFR Register
AUXR0
：
Auxiliary Register 0
SFR Page
= 0~F
SFR Address = 0xA1
Bit
7
6
5
4
3
2
1
0
Name
P60OC1
P60OC0
P60FD
PBKF
--
--
INT1H
INT0H
R/W
R/W
R/W
R/W
R/W
W
W
R/W
R/W
Reset Value
0
0
0
0
0
0
0
0
Bit 7~6: P6.0 function configured control bit 1 and 0. The two bits only act when internal RC oscillator
(IHRCO or ILRCO) is selected for system clock source. In external clock input mode, P6.0 is the
dedicated clock input pin. In internal oscillator condition, P6.0 provides the following selections for GPIO
or clock source generator. When P60OC[1:0] index to non-P6.0 GPIO function, P6.0 will drive the on-chip
RC oscillator output to provide the clock source for other devices.
P60OC[1:0]
P60
功能
I/O mode
00
P60
By P6M0.0
01
MCK
By P6M0.0
10
MCK/2
By P6M0.0
11
MCK/4
By P6M0.0
Please refer Section “9 System Clock” to get the more detailed clock information. For clock-out on
P6.0 function, it is recommended to set P6M0.0 to “1” which selects P6.0 as push-push output mode.
Bit 5: P60FD, P6.0 Fast Driving.
0: P6.0 output with default driving.
1: P6.0 output with fast driving enabled. If P6.0 is configured to clock output, enable this bit when
P6.0 output frequency is more than 12MHz at 5V application or more than 6MHz at 3V application.
Bit 4: PBKF, PWM termination flag. This bit is set by PWM termination source enabling. If this bit is set,
the enabled PWM channels 0~5 will be locked and the output pins will maintain the original GPIO state.
0: No PWM termination event occurs. Only cleared by software.
1: PWM termination event occurs or software triggers a PWM termination.
Bit 1: INT1H, INT1 high level/rising edge triggering enabling.
0: Reserve INT1 to trigger on low level or falling edge on the selected port pin.
1: Set INT1 to trigger on high level or rising edge on the selected port pin.
Bit 0: INT0H, INT0 high level/rising edge trigger enable.
0: Reserve INT0 to trigger on low level or falling edge on the selected port pin.
1: Set INT0 to trigger on high level or rising edge on the selected port pin.
AUXR1
：
Auxiliary Control Register 1
SFR Page
= 0~F
SFR Address = 0xA2
Bit
7
6
5
4
3
2
1
0
Name
--
--
CRCDS1
CRCDS0
--
--
--
DPS
R/W
W
W
R/W
R/W
W
W
W
R/W
Reset Value
0
0
0
0
0
0
0
0
Bit 7~6: Reserved. When AUXR1 is written, the software must write "0" to these bits.
Bit 5~4: CRCDS1~0. CRC0 data port selection 1~0.
Summary of Contents for CMT2380F17
Page 27: ...CMT2380F17 Rev0 1 27 347 www cmostek com 1 25 Phase Noise...
Page 177: ...CMT2380F17 Rev0 1 177 347 www cmostek com Figure 17 3 PCA Interrupt System...
Page 246: ...CMT2380F17 Rev0 1 246 347 www cmostek com SnMIPS S0MI S1MI 1 P3 3 P4 7...
