CMT2380F17
Rev0.1 | 172/347
www.cmostek.com
16.4.3
Global Control for all Timer Stop
TSPC0
：
Timer Stop Control Register 0
SFR Page
= 3 Only
SFR Address = 0x95 RESET= 0000-0000
Bit
7
6
5
4
3
2
1
0
Name
--
TL3SC
TL2SC
--
T3SC
T2SC
T1SC
T0SC
R/W
R/W
R/W
R/W
R/W
R/W
W
R/W
R/W
Reset Value
0
0
0
0
0
X
0
0
Bit 7:
Reserved. Software must write “0” on this bit when TSPC0 is written.
Bit 6, TL3SC, write “1” on this bit to set TR3L disabled (TR3L=0) when Timer 3 in split mode. This bit is
auto-
cleared by hardware after writing “1” operation. Write “0” on this bit is no action.
Bit 5, TL2SC, write “1” on this bit to set TR2L disabled (TR2L=0) when Timer 2 in split mode. This bit is
auto-
cleared by hardware after writing “1” operation. Write “0” on this bit is no action.
Bit 4: Reserved. Software must write “0” on this bit when TSPC0 is written.
Bit 3, T3SC, write “1” on this bit to set TR3 disabled (TR3=0). This bit is auto-cleared by hardware after
writing “1” operation. Write “0” on this bit is no action.
Bit 2, T2SC, write “1” on this bit to set TR2 disabled (TR2=0). This bit is auto-cleared by hardware after
writing “1” operation. Write “0” on this bit is no action.
Bit 1, T1SC, write “1” on this bit to set TR1 disabled (TR1=0). This bit is auto-cleared by hardware after
writing “1” operation. Write “0” on this bit is no action.
Bit 0, T0SC, write “1” on this bit to set TR0 disabled (TR0=0). This bit is auto-cleared by hardware after
writing “1” operation. Write “0” on this bit is no action.
Summary of Contents for CMT2380F17
Page 27: ...CMT2380F17 Rev0 1 27 347 www cmostek com 1 25 Phase Noise...
Page 177: ...CMT2380F17 Rev0 1 177 347 www cmostek com Figure 17 3 PCA Interrupt System...
Page 246: ...CMT2380F17 Rev0 1 246 347 www cmostek com SnMIPS S0MI S1MI 1 P3 3 P4 7...
