AN202
V1.0 | Page 47/73
www.cmostek.com
6.4
Brown-out Reset (BOR)
Low Voltage Reset is controlled by UCFG1<1:0> bit. Low voltage reset refers to the reset that the power
supply voltage is lower than the VBOR threshold voltage.However, low voltage reset may not occur when the
VDD voltage is lower than VBOR and the time does not exceed TBOR. The VBOR voltage needs to be
calibrated before the chip is shipped. The calibration can be completed by writing the internal calibration
register through the serial port. If the BOR (Brown-out Reset) is enabled (UCFG1<1:0>=00), the requirement
for the maximum VDD voltage rising time will not exist. The BOR circuit will control the chip in the reset status
until the VDD voltage exceeds the VBOR threshold voltage. It should be noted that the POR circuit does not
generate a reset signal when the VDD is lower than the threshold of the system that can work normally.If the
reset signal is generated by the BOR circuit, the VDD voltage must hold for more than 100us at the VSS level.
6.5
Error Instruction Reset
When the instruction register of CPU obtains the undefined instruction, the system will be reset. Using this
function can increase the anti-interference ability of the system.
6.6
Timeout Action
On power-up, the timeout sequence is as follows: PWRT timing is invoked after POR has expired. Since the
timing is invoked after POR has expired, the timeout event will occur if the /MCLR holds at a low level for a
long time. If /MCLR is pulled up, CPU will begin to execute immediately. This will be useful in the case of test
or multiple MCU synchronization.
PCON
（
Power Control Register
）
There are two status bits in the PCON register to indicate what type of Reset has occurred. Bit0 is the /BOR
bit, which is an unknown status on Power-on Reset, and the software must set it to 1 and check if it is 0. Bit1 is
the /POR bit, which is 0 on Power-on Reset, and the software must set it to 1.
Figure 6-3. Power-on Reset with MCLRB
1
2
3
4
5
6
7
8
9
10
VDD
POR_RSTN
4ms delay
BOOT_EN
PWRTE
BOOT_END
PWRT_OV
MCLRB
SYS_RSTN
PWRT,64ms
