AN202
V1.0 | Page 43/73
www.cmostek.com
POR or an exit from Sleep.
5.3.2
Two-Speed Start-up Sequence
1.
Wake-up from Power-on Reset or Sleep.
2.
Instructions begin execution by the internal oscillator at the frequency set in the IRCF<2:0> bit of the
OSCCON register.
3.
OST is enabled to count 1024 clock cycles.
4.
OST is timeout and waiting for the falling edge of the internal oscillator.
5.
OSTS is set to 1.
6.
The system clock is held low until the arrival of the next falling edge of the new clock (LP or XT mode).
7.
System clock is switched to external clock source.
5.4
Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) is designed to allow the device to continue to operate in the event of
anoscillator failure. FSCM can detect the oscillator failure at any time after the Oscillator Start-up Timer (OST)
has expired. FSCM can be enabled by setting the FCMEN bit in the Configuration Word register
（
UCFG1
）
to
1. FSCM can be used for all external oscillator modes (LP, XT and EC).
外部时钟
（
LP/XT/EC
）
Q
Q
SET
CLR
S
R
LFINTOSC
～
32KHz
分频器
/64
时钟故障信号
边沿触发寄存器
采样时钟产生
Figure 5-4. FSCM Schematic Block Diagram
5.4.1
Fail-Safe Detection
The FSCM module detects the oscillator fault by comparing the external oscillator with the FSCM sampling
clock. LFINTOSC divided by 64 is the sampling clock. Please see Figure 5-4. There is a latch inside the fault
detector. On each falling edge of the external clock, the latch is set to 1. On each rising edge of the sampling
clock, the latch is cleared. If the entire half cycle of the sampling clock has passed and the main clock is still
not in the low level, the fault is detected.
5.4.2
Fail-Safe Operation
When the external clock fault occurs, the FSCM switches the device clock to the internal clock source, and the
OSFIF flag bit of the PIR1 register is set to 1. If setting the OSFIF flag bit to 1while setting the OSFIE bit of the
