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Table 4-60. UCFG2Bit Function Description
4.1.31
PCL and PCLATH
The program counter (PC) is 11-bit.The lower 8-bit is from the PCL register, which is a readable and writable
register. The higher 3-bit (PC<10:8>) is not directly readable and writable, it is from PCLATH. On any reset,
PC will be cleared.The following figure shows the two situations for the loading of PC. Notice the LCALL and
LJUMP instructions on the right side of the figure. Because the operating code in the instruction is 11-bit, and
the PC of the chip is just 11-bit, so PCLATH is not needed.
10
8 7
0
/
PCLATH<2:0>
/
ALU
结果
3
8
PCH
PCL
PCLATH
10
8 7
0
/
OPCODE<10:0>
11
PCH
PCL
PCLATH
Instruction aimed at PCL LJUMP
、
LCALL instruction
Figure 4-1.PC Loading DiagraminDifferent Situations
Modify PCL
Executing any instruction with the PCL register as the destination simultaneously causes the Program
Counter PC<10:8> bits to be replaced by the contents of PCLATH register.This allows the entire contents of
the program counter to be changed by writing the desired high 3-bit to the PCLATH register.
A computed LJUMP instruction is accomplished by adding an offset to the program counter (ADDWR PCL).
Care should be exercised when jumping into the look-up table or the program branch table (computed LJUMP)
by modifying the PCL register. Assuming that PCLATH is set as the table start address, if the table length is
greater than 255 instruction, or if the lower 8-bit of memory address rolls over from 0xFF to 0x00 in the middle
of the table, then PCLATH must be incremented for each address rollover that occurs between the table
beginning and target location within the table.
Bit
Name
Function
7:4
-
Reserved-bit
3:0
LVDS[3:0]
Low voltage reset threshold selection
Value
Voltage
0010
1.8V
0011
2.0V
0100
2.2V
0110
2.8V
Others
Reserved
